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high performance hdmi?/dvi transmitter AD9889 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features hdmi/dvi transmitter compatible with hdmi 1.1 and hdcp 1.1 single 1.8 v power supply video/audio inputs are 3.3 v tolerant 80-lead, pb-free lqfp digital video 80 mhz operation supports all video formats from 480i to 1080i and 720p programmable 2-way color space converter supports rgb, ycbcr, ddr, itu656 formats auto input video format detection digital audio supports standard s/pdif for stereo or compressed audio up to 192 khz 8-channel lpcm i 2 s audio up to 192 khz special features for easy system design on-chip mpu to perform hdcp operations on-chip i 2 c master to handle edid reading 5 v tolerant i 2 c and mpd i/os, no extra device needed no audio master clock needed for s/pdif support applications dvd players and recorders digital set-top boxes av receivers digital cameras and camcorders functional block diagram register configuration logic sda clk vsync hsync de d[23:0] s/pdif mclk htpg scl tx0[1:0] tx1[1:0] tx2[1:0] txc[1:0] swing_adj i 2 s[3:0] ddsda ddcscl mda mcl color space conversion 4:2:2 to 4:4:4 conversion video data capture i 2 c master i 2 c slave hdcp controller hdcp cipher hdm itx core xor mask audio data capture AD9889 0 5 6 7 5 - 0 0 1 figure 1. general description the AD9889 is an 80 mhz, high-definition multimedia inter- face (hdmi tm 1.1) transmitter. it supports hdtv formats up to 1080i and 720p, and graphic resolutions up to xga (1024 768 @ 75 hz). with the inclusion of hdcp, the AD9889 allows the secure transmission of protected content as specified by the hdcp 1.1 protocol. the AD9889 supports both s/pdif and 8-channel i 2 s audio. its high fidelity 8-channel i 2 s can transmit either stereo or 7.1 surround audio at 192 khz. the s/pdif can carry stereo lpcm (linear pulse code modulation) audio or compressed audio including dolby? digital, dts?, and thx?. the AD9889 helps to reduce system design complexity and cost by incorporating such features as hdcp master, i 2 c master for edid reading, a single 1.8 v power supply, and 5 v tolerance on i 2 c and hot plug detect pins. fabricated in an advanced cmos process, the AD9889 is pro- vided in a space-saving, 80-lead, surface-mount, pb-free plastic lqfp and is specified over the 0c to 70c temperature range. evaluation kits and other resources evaluation kits, reference design schematics, software quick start guide, and codes are available from analog devices local sales and marketing personnel. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 2 of 48 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 evaluation kits and other resources ............................................ 1 revision history ............................................................................... 2 electrical specifications ................................................................... 3 absolute maximum ratings............................................................ 5 explanation of test levels ........................................................... 5 esd caution.................................................................................. 5 pin configuration and function descriptions............................. 6 i 2 c addresses ................................................................................ 8 list of reference documents...................................................... 8 format standards ......................................................................... 8 design guide..................................................................................... 9 general description..................................................................... 9 video data capture...................................................................... 9 input formats................................................................................ 9 4:2:2 to 4:4:4 data conversion.................................................. 14 horizontal sync, vertical sync, and degeneration................ 14 degeneration............................................................................... 14 hsync and vsync generation ............................................. 14 color space conversion matrix (csc) ................................... 16 audio data capture ....................................................................... 17 i 2 s audio...................................................................................... 17 s/pdif audio.............................................................................. 17 cts generation.......................................................................... 17 n parameter ................................................................................ 18 cts parameter............................................................................ 18 packet configuration................................................................. 19 pixel repetition .......................................................................... 19 hdcp handling......................................................................... 20 edid reading............................................................................. 20 interrupts..................................................................................... 20 power management ................................................................... 20 2-wire serial register map ........................................................... 21 2-wire serial control register detail chip identification ....... 33 source product description (spd) infoframe ....................... 37 2-wire serial control port ............................................................ 40 data transfer via serial interface............................................. 40 serial interface read/write examples ..................................... 41 pcb layout recommendations.................................................... 42 power supply bypassing ............................................................ 42 digital inputs .............................................................................. 42 color space converter (csc) common settings...................... 43 outline dimensions ....................................................................... 45 ordering guide .......................................................................... 45 revision history 10/05revision 0: initial version www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 3 of 48 electrical specifications table 1. AD9889kstz-80 parameter temp test level min typ max unit digital inputs input voltage, high (v ih ) full vi 1.4 v input voltage, low (v il ) full vi 0.7 v input current, high (v ih ) full v ?1.0 ma input current, low (v il ) full v +1.0 ma input capacitance 25c v 3 pf digital outputs output voltage, high (v oh ) full vi av dd ? 0.1 v output voltage, low (v ol ) full vi 0.4 v thermal characteristics jc junction-to-case thermal resistance v 25 c/w ja junction-to-ambient thermal resistance v 30 c/w ambient temperature full v 0 25 70 c dc specifications input leakage current, i il 25c vi ?10 +10 a input clamp voltage (?16 ma) 25c v ?0.8 v input clamp voltage (+16 ma) 25c v +0.8 differential high level output voltage v av cc v differential output short-circuit current v 10 a power supply v dd (all) supply voltage full iv 1.71 1.8 1.89 v v dd supply voltage noise full v 50 mv p-p complete power-down current (everything except i 2 c) 25c iv 6 13 ma quiet power down current (monitor detect on) 25c vi 7 ma transmitter supply current (27 mhz typical random pattern) 25c vi 165 ma transmitter supply current (80 mhz typical random pattern) 25c iv 185 205 ma transmitter total power (80 mhz single pixel stripe pattern; worst case operating conditions) full vi 430 mw ac specifications clk frequency 25c iv 13.5 80 mhz clk duty cycle 25c vi 40% 60% worst case clk input jitter full vi 1.0 ns setup time to clk falling edge vi tbd tbd ns hold time to clk falling edge vi tbd tbd ns tmds differential swing vii 800 1000 1200 mv vsync and hsync delay from de falling edge vi 1 ui vsync and hsync delay to de rising edge vi 1 ui de high time 25c vi 8191 ui de low time 25c vi 138 ui differential output swing low-to-high transition time 25c vii 75 490 ps differential swing output high-to-low transition time 25c vii 75 490 ps www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 4 of 48 AD9889kstz-80 parameter temp test level min typ max unit audio ac timing sample rate (i 2 s and s/pdif) full iv 32 192 khz i 2 s cycle time 25c iv 1 ui i 2 s setup time 25c iv 15 ns i 2 s hold time 25c iv 0 ns audio pipeline delay 25c iv 75 us www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 5 of 48 absolute maximum ratings table 2. parameter rating digital inputs 5 v to 0.0 v digital output current 20 ma operating temperature range ?40c to +85c storage temperature range ?65c to +150c maximum junction temperature 150c maximum case temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. explanation of test levels table 3. level test i 100% production tested. ii 100% production tested at 25c and sample tested at specified temperatures. iii sample tested only. iv parameter is guaranteed by design and characterization testing. v parameter is a typical value only. vi 100% production tested at 25c; guaranteed by design and characterization testing. vii limits defined by hdmi specification. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 6 of 48 pin configuration and fu nction descriptions 2 d0 3 de 4 hsync 7 s/pdif 6 clk 5 vsync 1 dv dd 8 mclk 9 i 2 s0 10 i 2 s1 12 i 2 s3 13 sclk 14 lrclk 15 gnd 16 pv dd 17 gnd 18 gnd 19 pv dd 20 pv dd 11 i 2 s2 59 58 57 54 55 56 60 53 52 gnd d15 d16 d19 d18 d17 gnd d20 d21 51 d22 49 mcl 48 mda 47 sda 46 scl 45 ddsda 44 ddcscl 43 gnd 42 gnd 41 av dd 50 d23 21 pv dd 22 gnd 23 ext_sw 24 av dd 25 hpd 26 gnd 27 txc? 28 txc+ 29 av dd 30 tx0? 31 tx0+ 32 gnd 33 pd/a0 34 tx1? 35 tx1+ 36 av dd 37 tx2? 38 tx2+ 39 gnd 40 int 80 gnd 79 gnd 78 d1 77 d2 76 d3 75 d4 74 d5 73 d6 72 d7 71 d8 70 d9 69 d10 68 d11 67 d12 66 d13 65 d14 64 dv dd 63 dv dd 62 dv dd 61 dv dd pin 1 AD9889 top view (not to scale) 05675-002 figure 2. pin configuration table 4. complete pinout list pin type pin no. mnemonic description value inputs 50 to 58, 65 to 78, 2 d[23:0] video data input 1.8 v cmos 6 clk video clock input 1.8 v cmos 3 de data enable bit for digital video 1.8 v cmos 4 hsync horizontal sync input 1.8 v cmos 5 vsync vertical sync input 1.8 v cmos 23 ext_sw differential output swing adjustment 1.8 v cmos 25 hpd hot plug detect signal 1.8 v cmos 7 s/pdif s/pdif (sony/philips digital interface) audio input pin 1.8 v cmos 8 mclk audio reference clock, 128 fs or 256 fs 1.8 v cmos 12 to 9 i 2 s[3:0] i 2 s audio data inputs 1.8 v cmos 13 sclk i 2 s audio clock 1.8 v cmos 14 lrclk left/right channel selection 1.8 v cmos 33 pd/a0 power-down control 1.8 v cmos outputs 28, 27 txc+ differential clock output tmds txc? differential clock output complement 38, 37 tx2+ differential output channel 2 tmds tx2? differential output channel 2 complement 35, 34 tx1+ differential output channel 1 tmds tx1? differential output channel 1 complement 31, 30 tx0+ differential output channel 0 tmds tx0? differential output channel 0 complement 40 int monitor sense connection status 1.8 v cmos www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 7 of 48 pin type pin no. mnemonic description value power supply 24, 29, 36, 41 av dd output power supply 1.8 v 1, 61, 62, 63, 64 dv dd digital and i/o power supply 1.8 v 16, 19, 20, 21 pv dd pll power supply 1.8 v 15, 17, 18, 22, 26, 32, 39, 42, 43, 59, 60, 79, 80 gnd ground 0 v control 47 sda serial port data i/o 3.3 v cmos 46 scl serial port data clock (100 khz maximum) 3.3 v cmos 48 mda serial port data i/o to hdcp keys 3.3 v cmos 49 mcl serial port data clock to hdcp keys 3.3 v cmos 45 ddsda serial port data i/o to receiver 3.3 v cmos 44 ddcscl serial port data clock to receiver 3.3 v cmos table 5. pin function descriptions pin mnemonic description outputs txc+ differential clock output at pixel clock rate; transition minimized differential signaling (tmds). txc? differential clock output complement. tx2+ differential output of the red da ta at 10 the pixel clock rate; tmds. tx2? differential red output complement. tx1+ differential output of the green da ta at 10 the pixel clock rate; tmds. tx1? differential green output complement. tx0+ differential output of the blue da ta at 10 the pixel clock rate; tmds. tx0? differential blue output complement. int monitor sense. serial port (2-wire) sda serial port data i/o. scl serial port data clock. ddsda serial port data i/o master to receiver. ddcscl serial port data clock master to receiver. mda serial port data i/o master to hdcp keys. mcl serial port data clock master to hdcp keys. for a full description of the 2-wire serial register and how it works, refer to the 2-wire serial control port section. inputs d[23:0] digital input in rgb or ycbcr format. clk video clock input. de data enable for video data. hsync horizontal sync input. vsync vertical sync input. this is the input for vertical sync. ext_sw swing adjust sets the differential output voltage or swin g. an 887 resistor (1% tolerance) should be placed between this pin and ground. hpd hot plug detect. this indicates to the interface whether the receiver is connected. s/pdif s/pdif audio input. this is the audio input from a sony/philips digital interface. mclk audio reference clock. set either to 128 fs or 256 fs. i 2 s[3:0] i 2 s audio inputs. these represent the eight channels of audio (two per input) available through i 2 s. i 2 s clk i 2 s audio clock. lrclk left/right channel selection. pd/a0 power down. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 8 of 48 pin mnemonic description power supply dv dd main power supply. these pins supply power to the main el ements of the circuit. they should be filtered and as quiet as possible. av dd output power supply pv dd clock generator power supply. the most sensitive portion of the AD9889 is the clock generation circuitry. these pins provide power to the clock pll (phase-locked loop) and help the user design for optimal performance. the designer should provide quiet, noise-free power to these pins. gnd ground. the ground return for all circuitry on-chip. it is recommended that the AD9889 be assembled on a single solid ground plane, with careful attention given to ground current paths. i 2 c addresses the sda/scl programming address is 0x72 or 0x7a based on whether a0 is pulled high (10 k resistor = 0x7a) or pulled low (10 k resistor = 0x72). the mda/mcl eeprom address is 0xa0. the edid eeprom on the receiver is expected to have an address of 0xa0. list of reference documents table 6. document description eia/cea-861b describes audio and video infoframes as well as the e-edid structure for hdmi. hdmi v1.1 defining document for hdmi version 1.1. can be located at www.hdmi.org. hdcpv1.0 defining document for hdcp version 1.1. can be located at www.digital-cp.com. itu-r bt.656-3 defining document for bt656. format standards in this document, data is represented in a variety of ways. table 7. data type format 0xnn hexadecimal (base-16) numbers are represented using the c language notation, preceded by 0x. 0bnn binary (base-2) numbers are represented us ing the c language notation, preceded by 0b. nn decimal (base-10) numbers are represented using no additional prefixes or suffixes. bit bits are numbered in little-endian format , that is, the least significant bit (lsb) of a byte or word is referred to as bit 0. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 9 of 48 design guide general description the AD9889 hdmi transmitter provides a high bandwidth digital content protected (hdcp) digital link between a wide range of digital input formatsboth audio and video (see table 8) and output formats (see table 9). video and audio data are captured and prepared for transmission while three separate i 2 c buses (two of which are masters) are used to program and provide content protection for the data to be transmitted. video data capture the AD9889 can accept video data from as few as eight pins (ycbcr ddr) representing 8-bit data or as many as 24 pins representing 12-bit data. the AD9889 is capable of detecting all of the 34 video formats defined in the eia/cea-861b specification. if video id (vid) 32, 33, or 34 is present, the user needs to set register r0x15[0] to 0b1, as these modes have v ref frequencies of 30 hz or less. the user can read the detected video format at r0x3e[7:2]. formats outside the eia/cea-861b specification can be read in r0x3f[7:5]. detailed line count differences for 240p and 288p modes can be read from r0x3f[4:3]. in order to distinguish between an aspect ratio of 4:3 and one of 16:9, r0x17[1] should be set accordingly. table 8. input formats supported no. of bits input format 12 rgb (ddr) 12 ycbcr 4:4:4 (ddr) 24 rgb 4:4:4 24 ycbcr 4:4:4 16 ycbcr 4:2:2 (itu.601) 20 ycbcr 4:2:2 (itu.601) 24 ycbcr 4:2:2 (itu.601) 8 ycbcr (ddr) 10 ycbcr (ddr) 12 ycbcr (ddr) 8 ycbcr 4:2:2 (itu.656) 10 ycbcr 4:2:2 (itu.656) 12 ycbcr 4:2:2 (itu.656) table 9. output formats supported no. of bits output format 24 rgb 4:4:4 24 ycbcr 4:4:4 16 ycbcr 4:2:2 20 ycbcr 4:2:2 24 ycbcr 4:2:2 input formats t setup t setup t hold t hold t hold input data: d(23:0), de, syncs input clock- rising edge 05675-014 figure 3. timing for data input www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 10 of 48 normal 4:4:4 input format (rgb or ycbcr) input id = 0 an input format of rgb 4:4:4 or ycbcr 4:4:4 can be selected by setting the input id (r0x15[3:1]) to 0b000. the input color spac e (cs) must be selected by setting r0x16[0] to 0b0 for rgb or 0b1 fo r ycbcr. there is no need to set the input style (r0x16[3:2]). table 10. data23:0 input format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rgb 4:4:4 r[7:0] g[7:0] b[7:0] ycbcr 4:4:4 cr[7:0] y[7:0] cb[7:0] ycbcr 4:2:2 formats (24 bits, 20 bits, or 16 bits) with separate sync, input id = 1 an input with ycbcr 4:2:2 with separate syncs can be selected by setting the input id (r0x15[3:1]) to 0b001. the input cs (r0x1 6[0]) must be set to 0b1 for proper operation. the data bit width (2 4 bits, 20 bits, or 16 bits) must be set with r0x16[5:4]. the thr ee input pin assignment styles are shown in table 11. the input style can be set in r0x16[3:2]. table 11. data 23:0 input format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 style 1 ycbcr 4:2:2 sep. cb[11:4] y[11:4] cb[3:0] y[3:0] sync (24 bit) cr[11:4] y[11:4] cr[3:0] y[3:0] ycbcr 4:2:2 sep. cb[9:2] y[9:2] cb[1:0] y[1:0] sync (20 bit) cr[9:2] y[9:2] cr[1:0] y[1:0] ycbcr 4:2:2 sep. cb[7:0] y[7:0] sync (20 bit) cr[7:0] y[7:0] style 2 24-bit cb[11:0] y[11:0] cr[11:0] y[11:0] 20-bit cb[9:0] y[9:0] cr[9:0] y[9:0] 16-bit cb[7:0] y[7:0] cr[7:0] y[7:0] style 3 24-bit y[11:0] cb[11:0] y[11:0] cr[11:0] 20-bit y[9:0] cb[9:0] y[9:0] cr[9:0] 16-bit y[7:0] cb[7:0] y[7:0] cr[7:0] www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 11 of 48 ycbcr 4:2:2 formats (24 bits, 20 bits, or 16 bits) with embedded syncs, input id = 2 an input with ycbcr 4:2:2 with embedded syncs can be selected by setting the input id (r0x15[3:1]) to 0b010. hs ync and vsync a re embedded as start of active video (sav) and end of active video (eav). the input cs (r0x16[0]) must be set to 0b1 for proper operation. the data bit width (24 = 12 bits, 20 = 10 bits, or 16 = 8 bits) must be set with r0x16[5:4]. the three input pin ass ignment styles are shown in table 12. the input style can be set in r0x16[3:2]. the only difference between input id 1 and input id 2 is that the syncs on id 2 are embedded in the data much like itu 656 running at 1 clock and double width. table 12. data 23:0 input format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stle 1 ycbcr 4:2:2 sep. cb[11:4] y[11:4] cb[3:0] y[3:0] sync (24 bit) cr[11:4] y[11:4] cr[3:0] y[3:0] ycbcr 4:2:2 sep. cb[9:2] y[9:2] cb[1:0] y[1:0] sync (20 bit) cr[9:2] y[9:2] cr[1:0] y[1:0] ycbcr 4:2:2 sep. cb[7:0] y[7:0] sync (16 bit) cr[7:0] y[7:0] style 2 24-bit cb[11:0] y[11:0] cr[11:0] y[11:0] 20-bit cb[9:0] y[9:0] cr[9:0] y[9:0] 16-bit cb[7:0] y[7:0] cr[7:0] y[7:0] style 3 24-bit y[11:0] cb[11:0] y[11:0] cr[11:0] 20-bit y[9:0] cb[9:0] y[9:0] cr[9:0] 16-bit y[7:0] cb[7:0] y[7:0] cr[7:0] ycbcr 4:2:2 formats (double data ra te) formats (12, 10, or 8 bits) wi th separate syncs, input id = 3 an input with ycbcr 4:2:2 ddr data and separate syncs can be selected by setting the input id (r0x15[3:1]) to 0b011. the input cs (r0x16 [0]) must be set to 0b1. the data bit width (12 bits, 10 bits, or 8 bits) must be set with r0x16[5:4]. the two input pin assignment styles are shown in table 13. the input style can be set in r0x16[3:2]. table 13. data 23:0 input format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stle 1 12-bit cb/y/cr/y[11:4] [3:0] 10-bit cb/y/cr/y[9:2] [1:0] 8-bit cb/y/cr/y[7:0] style 2 12-bit cb/y/cr/y[11:0] 10-bit cb/y/cr/y[9:0] 8-bit cb/y/cr/y[7:0] www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 12 of 48 ycbcr 4:2:2 ddr (double data rate) fo rmats (12 bits, 10 bits, or 8 bits) wi th embedded syncs. input id = 4 an input with ycbcr 4:2:2 ddr data and embedded syncs (itu 656) can be selected by setting the input id (r0x15[3:1]) to 0b100. the input cs (r0x16[0]) must be set to 0b1. the data bit width (12 bits, 10 bits, or 8 bits) must be set with r0x16[5:4]. the two i nput pin assignment styles are shown in table 14. the input style can be set in r0x16[3:2]. the order of data input is the order in the table (for example, 12-bit data is accepted as cb0, y0, cr0, y1, cb2, y2, cr2, y3). table 14. data 23:0 input format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stle 1 12-bit cb/y/cr/y[11:4] [3:0] 10-bit cb/y/cr/y[9:2] [1:0] 8-bit cb/y/cr/y[7:0] style 2 12-bit cb/y/cr/y[11:0] 10-bit cb/y/cr/y[9:0] 8-bit cb/y/cr/y[7:0] normal 4:4:4 input format (rgb or ycbcr) cloc ked at double data rate (ddr), input id = 5 an input with ycbcr 4:2:2 ddr data and separate syncs can be selected by setting the input id (r0x15[3:1]) to 0b011. the input cs (r0x16[0]) must be set to 0b1. the data bit width (12 bits, 10 bi ts, or 8 bits) must be set with r0x16[5:4]. the three input pi n assignment styles are shown in table 15. the input style can be set in r0x16[3:2]. table 15. data 23:0 input format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stle 1 g[3:0] b[7:0] rgb 4:4:4 (ddr) (1 st edge, 2 nd edge) r[7:0] g[7:4] y[3:0] cb[7:0] ycbcr 4:4:4 (ddr) (1 st edge, 2 nd edge) cr[7:0] y[7:4] style 2 r[7:0] g[7:4] rgb 4:4:4 (ddr) (1 st edge, 2 nd edge) g[3:0] b[7:0] cr[7:0] y[7:4] ycbcr 4:4:4 (ddr) (1 st edge, 2 nd edge) y[3:0] cb[7:0] style 3 y[7:0] cb[7:4] ycbcr 4:4:4 (ddr) (1 st edge, 2 nd edge) cb[3:0] cr[7:0] www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 13 of 48 ycbcr 4:2:2 formats (24, 20, or 16 bits) ddr with separate sync, input id = 6 an input format of ycbcr 4:2:2 ddr can be selected by setting the input id (r0x15[3:1]) to 0b110. the three different input pin assignment styles are shown in table 16. the input style can be set in r0x16[3:2]. the input cs (r0x16[0]) must be set to 0b1. the data bit width (12, 10, or 8 bits) must be set to with r0x16[5:4]. the 1 st or the 2 nd edge may be the rising or falling edge. the data input edge is defined in r0x16[1]. 0b0 = rising edge; 0b1 = falling edge. pixel 0 is the first pixel of the 4:2:2 word and should be where de starts. table 16. data23:0 input format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 stle 1 1 st edge y[7:4] cb[3:0] y[3:0] 1 st pixel 2 nd edge cb[11:4] y[11:8] y[7:4] cr[3:0] y[3:0] ycbcr 4:2:2 sep syncs (ddr) 12-bit 2 nd pixel cr[11:4] y[11:8] y[5:4] cb[3:0] y[3:0] cb[9:4] y[9:6] y[5:4] cr[3:0] y[3:0] ycbcr 4:2:2 sep syncs (ddr) 10-bit cr[9:4] y[9:6] cb[3:0] y[3:0] cb[7:4] y[7:4] cr[3:0] y[3:0] ycbcr 4:2:2 sep. syncs (ddr) 8-bit cr[7:4] y[7:4] style 2 y[11:0] cb[11:0] y[11:0] 12-bit cr[11:0] y[9:0] cb[9:0] y[9:0] 10-bit cr[9:0] y[7:0] cb[7:0] y[7:0] 8-bit cr[7:0] style 3 cb[11:0] y[11:0] cr[11:0] 12-bit y[11:0] cb[9:0] y[9:0] cr[9:0] 10-bit y[9:0] cb[7:0] y[7:0] cr[7:0] 8-bit y[7:0] www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 14 of 48 4:2:2 to 4:4:4 data conversion the AD9889 has the ability to convert ycbcr video from 4:4:4 to 4:2:2 and 4:2:2 to 4:4:4. to convert from 4:4:4 to 4:2:2, the video data goes through a filter first to remove any artificial downsampling noise. to convert from 4:2:2 to 4:4:4, the AD9889 utilizes either the zero-order upconversion (pixel repetition) or first-order upconversion (linear interpolation). the upconversion and downconversion are used when the video output timing format does not match the video input timing format. the video output format is set by register r0x16[7:6]. the video input format is set by the video id (r0x15[3:1]) and video color space (r0x16[0]). the default mode for upconversion is pixel repetition. to use linear interpolation, set register r0x17[2] to 1. horizontal sync, vertical sync, and degeneration when transmitting video data across the tmds interface, it is necessary to have an hsync, vsync, and data enable (de) defined for the image. itu-656 based sources have start of active video (sav) and end of active video (eav) signals built in, but the hsync and vsync must be generated (the de is implied by the sav and eav signals). other sources (with separate syncs) have hsync, vsync, and de supplied at the same time as the pixel data. degeneration the AD9889 offers a choice of de from an external pin, or an internally generated de. to activate the internal de generation, set register r0x17[0] to 1. register r0x35 to register r0x3a are used to define the de. r0x35 and r0x36[7:6] define the number of pixels from the hs leading edge to the de leading edge. r0x36[5:0] are the number of hsyncs between the leading edge of vs and de. r0x37[7:5] defines the difference of hs counts during vs blanking for interlace video. r0x37[4:0] and r0x38[7:1] indicate the width of the de. r0x39 and r0x3a[7:4] are the number of lines of active video (see figure 4). hsync and vsync generation for video with embedded hsync and vsync, such as eav and sav, found in itu 656 format, it is necessary to reconstruct hsync and vsync. this is done with register r0x30 to register r0x34. r0x30 and r0x31[7:6] specify the number of pixels between the hsync leading edge and the trailing edge of de. register r0x31[5:0] and register r0x32[7:4] are the duration of the hsync in pixel clocks. r0x32[3:0] and r0x33[7:2] are the number of hs pulses between the trailing edge of the last de and the leading edge of the vsync pulse. register r0x33[1:0] and register r0x34[7:0] are the duration of vsync in units of hsyncs. hsync and vsync polarity can be specified by setting r0x17[6] (for vsync) and r0x17[5] (for hsync). 05675-004 hs delay r0x35, r0x36[7:6] vs delay r0x36[5:0] width r0x37[4:0], r0x38[7:1] height r0x39, r0x3a[7:4] active video figure 4. active video www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 15 of 48 05675-005 a b a: hsync placement r0x30, r0x31[7:6] b: hsync duration r0x31[5:0], r0x32[7:4] eav hsync sav figure 5. hsync reconstruction 05675-006 ab a: vsync placement r0x32[3:0], r0x33[7:2] b: vsync duration r0x33[1:0], r0x34 eav vsync sav figure 6. vsync reconstruction 05675-008 4096 1 2 2 1 0 4 + + + a1[12:0] r in [11:0] 4096 1 a2[12:0] b in [11:0] 4096 1 a3[12:0] g in [11:0] csc_mode[1:0] r out [11:0] a4[12:0] figure 7. single csc channel www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 16 of 48 color space conversion matrix (csc) the color space conversion matrix in the AD9889 consists of three identical processing channels. in each channel, three input values are multiplied by three separate coefficients. also included are an offset value for each row of the matrix and a scaling multiple for all values. each value is 13-bit, twos complement resolution to ensure the signal integrity is maintained. the csc is designed to run at speeds up to 80 mhz supporting resolutions up to 1080i at 60 hz and uxga at 60 hz. with any-to-any color space support, rgb, yuv, ycbcr, and other formats are supported by the csc. the main inputs, r in , g in , and b in come from the 8-bit to 12-bit inputs from each channel. these inputs are based on the input format detailed in table 10 to table 16. the mapping of these inputs to the csc inputs is shown in table 17. table 17. csc port mapping input channel csc input channel r/cr r in gr/y g in b/cb b in one of the three channels is represented in figure 7. in each processing channel the three inputs are multiplied by three separate coefficients marked a1, a2, and a3. these coefficients are divided by 4096 to obtain nominal values ranging from ?0.9998 to +0.9998. the variable labeled a4 is used as an offset control. the csc_mode setting is the same for all three processing channels. this multiplies all coefficients and offsets by a factor of 2csc_mode. the functional diagram for a single channel of the csc as per figure 7 is repeated for the remaining g and b channels. the co- efficients for these channels are b1, b2, b3, b4, c1, c2, c3, and c4. a programming example and register settings for several common conversions are listed in the color space converter (csc) common settings section. for a detailed functional description and more programming examples, refer to an-795, the ad9880 color space converter user's guide . www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 17 of 48 audio data capture the AD9889 is capable of receiving audio data in either i 2 s or s/pdif format for packetization and transmission over the hdmi interface. i 2 s audio the AD9889 can accommodate from two to eight channels of i 2 s audio at up to a 192 khz sampling rate. selection of i 2 s audio mode (vs. s/pdif) is set with r0x0a[4] = 0. the detected sampling frequency (from 32 khz to 192 khz) can be read in r0x04[7:4]. the output sampling frequency (from 32 khz to 192 khz) can be selected with r0x15[7:4]. the number of channels and the specific channels can be selected in r0x0c[5:2] and r0x50[7:5]. if all eight channels (i 2 s0 to i 2 s3) are required, setting all bits or r0x0c[5:2] to 1 selects eight channels. if i 2 s0 only is needed, setting r0x0c[2] to 1 selects this. the placement of these packets with respect to their output can be specified in register r0x0e to register r0x11. default settings place all channels in their respective position (i 2 s0 left channel in channel 0 left position, i 2 s3 right channel in channel 3 right position), but this mapping is completely programmable. the AD9889 supports standard i 2 s, left-justified i 2 s, and right- justified i 2 s formats via r0x0c[1:0] and sample word lengths between 16 bits and 24 bits (r0x14[3:0]). s/pdif audio the AD9889 is capable of accepting two channel lpcm and encoded audio up to a 192 khz sampling rate via the s/pdif. s/pdif audio input is selected by setting r0x0a[4] = 1. the AD9889 is capable of accepting s/pdif with or without an mclk input. when no mclk is present, the AD9889 makes the determination of the cts value (n/cts determines the mclk frequency). cts generation audio data being carried across the hdmi link, which is driven by a tmds (video) clock only, does not retain the original audio sample clock. the task of recreating this clock at the sink is called audio clock regeneration. there are a variety of clock regeneration methods that can be implemented in an hdmi sink, each with a different set of performance characteristics. the hdmi specification does not attempt to define exactly how these mechanisms operate. it does, however, present a possible configuration and it does define the data items that the hdmi source supplies to the hdmi sink in order to allow the hdmi sink to adequately regenerate the audio clock. it also defines how that data is generated. in many video source devices, the audio and video clocks are generated from a common clock (coherent clocks). in this situation, there exists a rational (integer divided by integer) relationship between these two clocks. the hdmi clock regeneration architecture can take advantage of this rational relationship and can also work in an environment where there is no such relationship between these two clocks, that is, where the two clocks are truly asynchronous or where their relationship is unknown. figure 8 shows the system architecture model used by hdmi for audio clock regeneration. the source determines the fractional relationship between the video clock and an audio reference clock (128 audio sample rate) and passes the numerator and denominator for that fraction to the sink across the hdmi link. the sink can then recreate the audio clock from the tmds clock by using a clock divider and a clock multiplier. the exact relationship between the two clocks is 128 fs = f tmds _clock n/cts the source determines the value of the numerator n as stated in section 7.2.1 of the hdmi specification. typically, this value n is used in a clock divider to generate an intermediate clock that is slower than the 128 fs clock by the factor n. the source typically determines the value of the denominator cycle time stamp (cts) by counting the number of tmds clocks in each of the 128 fs/n clocks. 05675-007 divide by n divide by cts cts 1 n 1 tmds clock v ideo cloc k n 128 f s 128 f s sink device source device 1 n and cts values are transmitted using the ?audio clock regeneration? packet. video clock is transmitted on tmds clock channel. register n multiply by n cycle time counter figure 8. audio clock regeneration www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 18 of 48 n parameter n shall be an integer number that meets the following restriction: 128 fs/1500 hz n 128 fs/300 hz with a recommended optimal value of 128 fs/1000 hz equals n. for coherent audio and video clock sources, use table 18 to table 20 to determine the value of n. for noncoherent sources or sources where coherency is not known, use the equations previously described. cts parameter cts is an integer number that satisfies the following: ( average ct s value ) = ( f tmds _clock n )/(128 fs) recommended n and expected cts values the recommended value of n for several standard pixel clocks is given in table 18 to table 20. it is recommended that sources with noncoherent clocks use the values listed for the pixel clock type labeled other. table 18. recommended n and expected cts values for 32 khz audio 32 khz pixel clock (mhz) n cts 25.1/1.001 4576 28125 25.2 4096 25200 27 4096 27000 27 1.001 4096 27027 54 4096 54000 54 1.001 4096 54054 74.25/1.001 11648 210937 to 210938 1 74.25 4096 74250 148.5/1.001 11648 421875 148.5 4096 148500 other 4096 measured 1 this value alternates becaus e of the restriction on n. table 19. recommended n and expected cts values for 44.1 khz audio and multiples 44.1 khz 88.2 khz 176.4 khz pixel clock (mhz) n cts n cts n cts 25.1/1.001 7007 31250 14014 31250 28028 31250 25.2 6272 28000 12544 28000 25088 28000 27 6272 3000 12544 30000 25088 30000 27 1.001 6272 30030 12544 30030 25088 30030 54 6272 60000 12544 60000 25088 60000 54 1.001 6272 60060 12544 60060 25088 60060 74.25/1.001 17836 234375 35672 234375 71344 234375 74.25 6272 82500 12544 82500 25088 82500 148.5/1.001 8918 234975 17836 234375 35672 123375 148.5 6272 165000 12544 16500 25088 162000 other 6272 measured 15244 measured 25088 measured table 20. recommended n and expected ct s values for 48 khz audio and multiples 44.1 khz 88.2 khz 176.4 khz pixel clock (mhz) n cts n cts n cts 25.1/1.001 6864 28125 13728 28125 27456 28125 25.2 6144 25200 12288 25200 24576 25200 27 6144 27000 12288 27027 24576 27027 27 1.001 6144 27027 12288 27027 24576 27027 54 6144 54000 12288 54000 24576 54000 54 1.001 6144 54054 12288 54054 24576 74250 74.25/1.001 11648 140625 23296 140625 46592 140625 74.25 6144 74250 12288 74250 24576 74250 148.5/1.001 5824 140625 11648 140625 23296 140625 148.5 6144 148500 12288 148500 24576 148500 other 6144 measured 12288 measured 24576 measured www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 19 of 48 the AD9889 has two modes for cts generation: manual mode and auto mode. in manual mode, the user can program the cts number directly into the chip (r0x07 to r0x09) and select this external mode by setting r0x0a[7] to 1. in auto mode, the chip computes the cts based on the actual audio and video rates. this can be selected by setting r0x0a[7] to 0, and the results can be read from r0x04 to r0x06. manual mode is good for coherent audio and video, where the audio and video clock are generated from the same crystal; thus cts should be a fixed number. the auto mode is good for incoherent audio-video, where there is no simple integer ratio between the audio and video clock. a filter is available (r0x0a[6:5]) to stabilize the chip-generated cts. the 20-bit n value can be programmed into the AD9889 in register r0x01 to register r0x03. packet configuration the AD9889 supports all the packets listed in the hdmi 1.1 specification. each packet can be separately enabled and dis- abled. based on the audio and video input, the packets are added to the hdmi link at the earliest time, so that a minimum delay is incurred. notice the isrc1 packet has one bit to enable the isrc2 packet. for the general control packet, remember to clear or reset the bits to avoid system lock-up. pixel repetition due to hdmi specification and bandwidth requirements, sometimes it is necessary to set clock multiplication by 2 and 4 in order to maintain the minimum tmds clock frequency. the AD9889 offers three choices for the user to implement this function: auto mode, manual mode, and max mode (r0x3b[6:5]). for the auto mode (r0x3b[6:5] = 00), based on the input video format (either programmed by user, or chip detection) and audio sampling rate, AD9889 automatically sets the pixel repetition factor (r0x3d[7:6]). for manual mode (r0x3b[6:5] = 1), the user programs the pixel repetition factor in r0x3b[4:3]. for max mode (r0x3b[6:5] = 01), based on the input video format, the AD9889 selects the maximum repetition factor. the advantage of the max mode is that it is independent of the audio sampling rate. table 21. pixel repetitionvalid pixe l repeat values for each format video code video description eia/cea-861b pixel repeat values hdmi pixel repeat values 1 640 480p @ 60 hz no repetition no repetition 2, 3 720 480p @ 59.94/60 hz no repetition no repetition 4 1280 720p @ 59.94/60 hz no repetition no repetition 5 1920 1080i @ 59.94/60 hz no repetition no repetition 6, 7 720/1440 480i @ 59.94/60 hz pixel sent 2 times pixel sent 2 times 8, 9 720/1440 240p @ 59.94/60 hz pixel sent 2 times pixel sent 2 times 10, 11 2880 480i @ 59.94/60 hz pixel sent 0 to 10 times pixel sent 1 to 10 times 12, 13 2880 240p @ 59.94/60 hz pixel sent 1 to 10 times pixel sent 1 to 10 times 14, 15 1440 480p @ 59.94/60 hz no repetition pixel sent 1 to 2 times 1 16 1920 1080p @ 59.94/60 hz no repetition no repetition 17, 18 720 576p @ 50 hz no repetition no repetition 19 1280 720p @ 50 hz no repetition no repetition 20 1920 1080i @ 50 hz no repetition no repetition 21, 22 720/1440 576i @ 50 hz pixel sent 2 times pixel sent 2 times 23, 24 720/1440 288p @ 50 hz pixel sent 2 times pixel sent 2 times 25, 26 2880 576i @ 50 hz pixel sent 1 to 10 times pixel sent 1 to 10 times 27, 28 2880 288 @ 50 hz pixel sent 1 to 10 times pixel sent 1 to 10 times 29, 30 1440 576p @ 50 hz no repetition pixel sent 1 to 2 times 1 31 1920 1080p @ 50 hz no repetition no repetition 32 1920 1080p @ 23.97/24 hz no repetition no repetition 33 1920 1080p @ 25 hz no repetition no repetition 34 1920 1080p @ 29.9/30 hz no repetition no repetition 1 denotes change from eia/cea-861b valid values. pixel repetition is required to support some audio formats at 720 480p and 72 0 576p video format timings. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 20 of 48 hdcp handling the AD9889 has a built-in microcontroller to handle hdcp transmitter states, including handling downstream hdcp repeaters. to activate hdcp from a system level, the main controller needs to set r0xaf[7] to 1 to inform AD9889 that the video stream should be encrypted. the AD9889 takes control from there and implements all remaining tasks defined by the hdcp 1.1 specification. the system controller should monitor the status of hdcp by reading register r0xb8[6] (indicating the hdcp link has been established). there are also some error flags (r0xc5[7] and r0xc8[7:4]) to help debug the system. the AD9889 also supports av functions to suspend hdcp temporarily. to set av mute, clear r0x45[7] and set r0x45[6] to 1. to clear av mute, clear r0x45[6] and set r0x45[7] to 1. (note that it is invalid to set the two mute bits at the same time.) for more information, refer to application note an-810, edid and hdcp controller user guide for the AD9889 . edid reading the AD9889 has an i 2 c master (ddc pin 44 and pin 45) to read the edid based on system need. it buffers segment 0 once hpd is detected. the system can request other segments by programming register r0xc4. an interrupt bit (r0x96[2]) indicates the completion of edid rebuffering. to read edid data from the AD9889, use the AD9889 programming bus (pin 46 and pin 47) with i 2 c address 0x7e. this is the default address but can be changed by writing the desired address into register r0x43. for more information, refer to application note an-810, edid and hdcp controller user guide for the AD9889 . interrupts the AD9889 has interrupts to help with the system design: hot plug detection, receiver sense, vs detection, audio fifo overflow, itu 656 error, edid ready, hdcp error, and bksv ready. interrupts can be cleared by writing 1 into the interrupt register (r0x96, r0x97). there are read-only registers (r0xc5, r0xc6) to show the state of these signals. masks (r0x94, r0x95) are available to let the user selectively activate each interrupt. to enable a specific interrupt register, write 1 to the corresponding mask bit. power management the AD9889 power-down pin polarity depends on the AD9889s i 2 c address selection. to use 0x72, the pd pin is high active. to use 0x7a, the pd pin is low active. at any time, the power-down pin polarity can be verified by reading register r0x42[7]. the AD9889 can be powered down or reset either by pin 33 or by register r0x41[6]. during power-down mode, all the circuits are inactive except the i 2 c slave and some circuits related to mode and activity detection. during power-down mode, the chip status can still be read through the i 2 c slave. to enter normal power-down mode, either drive pin 33 to 1, or set r0x41[6] to 1. to further reduce power consumption, disable the receiver sense detection by setting register r0xa4[2] to 1. for hdcp security reasons, the i 2 c power-down bit is also reset by the power-down pin. anytime after power down, the user needs to drive the pd pin back to 0 and set r0x41[6] to 0 to activate the chip. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 21 of 48 2-wire serial register map the AD9889 is initialized and controlled by a set of registers that determine the operating modes. an external controller is em ployed to write and read the control registers through the two-line serial interface port. table 22. control register map hex address read/write or read only bits default value register name description 0x00 read [7:0] 00000000 chip revision revision of the chip, start from 0. 0x01 read/write [3:0] ****0000 n[19:16] 20-bit n used with cycle time stamp (cts) (see table 18 to table 20 for appropriate settings) to regenerate the audio clock in the receiver. for remaining bits, see r0x02 and r0x03. us ed only with i 2 s audio, not s/pdif. 0x02 read/write [7:0] 00000000 n[15:8] the middle byte of n. 0x03 read/write [7:0] 00000000 n[7:0] the lower byte of n. [7:4] 0000**** s/pdif_sf s/pdif sampling frequency for s/pdif audio decoded from hardware. this information is used by both the audio rx and the pixel repetition. 0011 = 32 khz. 0000 = 44.1 khz. 0010 = 48 khz. 1000 = 88.2 khz. 1010 = 96 khz. 1100 = 176.4 khz. 1110 = 192 khz. default = 0x0. 0x04 read [3:0] ****0000 cts_int[19:16] cts measured (internal). this 20-bit value is used in the receiver with the n value to regenerate an audio clock. for remaining bits, see r0x05 and r0x06. 0x05 read [7:0] 00000000 cts_int[15:8] middle byte of measured cts. 0x06 read [7:0] 00000000 cts_int[7:0] low byte of measured cts. 0x07 read/write [3:0] ****0000 cts_ext[19:16] cts (external). this 20-bit value is used in the receiver with the n value to regenerate an audio clock. for remaining bits see r0x08 and r0x09. 0x08 read/write [7:0] 00000000 cts_ext[15:8] middle byte of external cts. 0x09 read/write [7:0] 00000000 cts_ext[7:0] low byte of external cts. [7] 0******* cts_sel cts source select. 0 = internal cts. 1 = external cts. default = 0. [6:5] *10***** avg_mode cts filter mode. 00 = no filter. 01 = divide by 4. 10 = divide by 8. 11 = divide by16. default = 10. [4] ***0**** audio_sel audio type select. 0 = i 2 s. 1 = s/pdif. default = 0. [3] ****0*** mclk_sp mclk for s/pdif. 1 = mclk active. 0 = mclk inactive. default = 0. [2] *****0** mclk_i 2 s mclk for i 2 s. 1 = i 2 s mclk active. 0 = i 2 s mclk inactive. default = 0. 0x0a read/write [1:0] ******01 mclk_ratio mclk ratio. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 22 of 48 hex address read/write or read only bits default value register name description 00 = 128 fs. 01 = 256 fs. 10 = 384 fs. 11 = 512 fs. default = 01. [6] *0****** mclk_pol mclk polarity. 0 = rising edge. 1 = falling edge. default = 0. 0x0b read/write [5] **0***** flat_line flat line. 1 = flat line audio (audio sample not valid). 0 = normal. default = 0. [4:0] ****0111 test bits must be set to 0x7 for proper operation. [5:2] **1111** i 2 s enable i 2 s enable for the four i 2 s pins (active). 0001 = i 2 s0. 0010 = i 2 s1. 0100 = i 2 s2. 1000 = i 2 s3. default = 1111 for all. 0x0c read/write [1:0] ******00 i 2 s format i 2 s format. 00 = standard i 2 s mode. 01 = right-justified i 2 s mode. 10 = left-justified i 2 s mode. 11 = raw iec60958 mode. default = 0. 0x0d read/write [4:0] ***11000 i 2 s_bit_width i 2 s bit width. for right justified audio only. default is 24. not valid for widths greater than 24. [5:3] **000*** subpkt0_l_src registers 0x0e-0x11 should be set based on the speaker mapping information obtained from edid source of sub packet 0, left channel. default = 000. 0x0e read/write [2:0] *****001 subpkt0_r_src source of sub packet 0, right channel. default = 001. [5:3] **010*** subpkt1_l_src source of sub packet 1, left channel. default = 010. 0x0f read/write [2:0] *****011 subpkt1_r_src source of sub packet 1, right channel. default = 011. [5:3] **100*** subpkt2_l_src source of sub packet 2, left channel. default = 100. 0x10 read/write [2:0] *****101 subpkt2_r_src source of sub packet 2, right channel. default = 101. [5:3] **110*** subpkt3_l_src source of sub packet 3, left channel. default = 110. 0x11 read/write [2:0] *****111 subpkt3_r_src source of sub packet 3, right channel. default = 111. [5] **0***** cr_bit copyright bit. 0 = copyright. 1 = not copyright protected. [4:2] ***000** a_info additional information for channel status bits. 000 = 2 audio channels without pre-emphasis. 100 = 2 audio channels with 50/15 s pre-emphasis. 010 = reserved. 110 = reserved. default = 000. 0x12 read/write [1:0] ******00 clk_acc clock accuracy. 00 = level ii, normal accuracy 1000 10 -6 . 01 = level iii, variable pitch shifted clock. 10 = level i, high accuracy 50 10 -6 . 11 = reserved. default = 00. 0x13 read/write [7:0] 00000000 category code category code for audio infoframe; see iec 60958. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 23 of 48 hex address read/write or read only bits default value register name description [7:4] 0000**** source number source number. 0x14 read/write [3:0] ****0000 word length audio word length. 0000 = not specified. 0100 = 16 bits. 0011 = 17 bits. 0010 = 18 bits. 0001 = 19 bits. 0101 = 20 bits. 1000 = not specified. 1100 = 20 bits. 1011 = 21 bits. 1010 = 22 bits. 1001 = 23 bits. 1101 = 24 bits. default = 0x0. [7:4] 0000**** i 2 s_sf sampling frequency for i 2 s audio. this information is used by both the audio rx and the pixel repetition. 0011 = 32 khz. 0000 = 44.1 khz. 0010 = 48 khz. 1000 = 88.2 khz. 1010 = 96 khz. 1100 = 176.4 khz. 1110 = 192 khz. default = 0x0. [3:1] ****000* vfe_input_id input video format. 000 = rgb and ycbcr 4:4:4 (y on green). 001 = ycbcr 4:2:2; 16, 20, and 24 bit. 010 = same as 001 with hs and vs embedded as sav and eav. 011 = itu656 with separated syncs. 100 = itu656 with embedded syncs. 101 = ddr rgb 4:4:4 or ycbcr 4:4:4. 110 = ddr ycbcr 4:2:2. 111 = undefined. default = 000. 0x15 read/write [0] *******0 low_frq_video video refresh rate. 0 = v ref > 30 hz. 1 = v ref 30 hz refresh rate video. default = 0. 0x16 read/write [7:6] 00****** vfe_out_fmt video output format. this should be written along with r0x45[5:4]. 00 = rgb 4:4:4. 01 = ycbcr 4:4:4. 1x = ycbcr 4:2:2. default = 00. [5:4] **00**** vfe_422_width 4:2:2 input, could be either 8 bit, 10 bit, or 12 bit. x0 = 12 bits. 01 = 10 bits. 11 = 8 bits. default = 00. [3:2] ****00** vfe_input_style styles refer to the input pin assignments. see table 23 to table 28. x0 = style 1. 01 = style 2. 11 = style 3. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 24 of 48 hex address read/write or read only bits default value register name description [1] ******0* vfe_input_edge video data input edge. defines the first clock edge of video word clocked. 0 = rising edge. 1 = falling edge. default = 0 (in reference to ddr). [0] *******0 vfe_input_cs video input color space. 0 = rgb. 1 = ycbcr. default = 0. [7] 0******* itu_error_correct_en itu656 error correction. this must be enabled if using itu656 format. 0 = disable. 1 = enable. default = 0. [6] *0****** itu_vsync_pol vs polarity from regenerated itu 656 input. 0 = high polarity. 1 = low polarity. default = 0. [5] **0***** itu_hsync_pol hs polarity from regenerated itu 656 input. 0 = high polarity. 1 = low polarity. default = 0. [4:3] ***00*** csc_mode sets the fixed point position of the csc coefficients, including the a4, b4, and c4 offsets. 00 = 1.0, ?40964095. 01 = 2.0, ?81928190. 1 = 4.0, ?1638416380. default = 000. [2] *****0** gen_444_en 4:2:2 to 4:4:4 upconversion mode. 1 = uses interpolation. 0 = no interpolation. default = 0. [1] ******0* asp_ratio aspect ratio of input video. 0 = 4:3. 1 = 16:9. default = 0. 0x17 read/write [0] *******0 degen_en enable de generator. the de generator should be enabled when a de input is not provided. 1 = enable de generator. default = 0 (see register 0x30 to register 0x3a). 0x18 read/write [4:0] ***00110 csc_a1_msb msb of r0x19. 0x19 read/write [7:0] 01100010 csc_a1_lsb color space converter (csc) coefficient for equation: r out = ( a1 r in ) + (a2 g in ) + (a3 b in ) + a4 g out = (b1 r in ) + (b2 g in ) + (b3 b in ) + b4 b out = (c1 r in ) + (c2 g in ) + (c3 b in ) + c4 0x1a read/write [4:0] ***00100 csc_a2_msb msb of r0x1b. 0x1b read/write [7:0] 10101000 csc_a2_lsb csc coefficient for equation: r out = (a1 r in ) + ( a2 g in ) + (a3 b in ) + a4 g out = (b1 r in ) + (b2 g in ) + (b3 b in ) + b4 b out = (c1 r in ) + (c2 g in ) + (c3 b in ) + c4 0x1c read/write [4:0] ***00000 csc_a3_msb msb of r0x1d. 0x1d read/write [7:0] 00000000 csc_a3_lsb csc coefficient for equation: r out = (a1 r in ) + (a2 g in ) + ( a3 b in ) + a4 g out = (b1 r in ) + (b2 g in ) + (b3 b in ) + b4 b out = (c1 r in ) + (c2 g in ) + (c3 b in ) + c4 0x1e read/write [4:0] ***11100 csc_a4_msb msb of r0x1f. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 25 of 48 hex address read/write or read only bits default value register name description 0x1f read/write [7:0] 10000100 csc_a4_lsb csc coefficient for equation: r out = (a1 r in ) + (a2 g in ) + (a3 b in ) + a4 g out = (b1 r in ) + (b2 g in ) + (b3 b in ) + b4 b out = (c1 r in ) + (c2 g in ) + (c3 b in ) + c4 0x20 read/write [4:0] ***11100 csc_b1_msb msb of r0x21. 0x21 read/write [7:0] 10111111 csc_b1_lsb csc coefficient for equation: r out = (a1 r in ) + (a2 g in ) + (a3 b in ) + a4 g out = ( b1 r in ) + (b2 g in ) + (b3 b in ) + b4 b out = (c1 r in ) + (c2 g in ) + (c3 b in + c4 0x22 read/write [4:0] ***00100 csc_b2_msb msb of r0x23. 0x23 read/write [7:0] 10101000 csc_b2_lsb csc coefficient for equation: r out = (a1 r in ) + (a2 g in ) + (a3 b in ) + a4 g out = (b1 r in ) + ( b2 g in ) + (b3 b in ) + b4 b out = (c1 r in ) + (c2 g in ) + (c3 b in ) + c4 0x24 read/write [4:0] ***11110 csc_b3_msb msb of r0x25. 0x25 read/write [7:0] 01110000 csc_b3_lsb csc coefficient for equation: r out = (a1 r in ) + (a2 g in ) + (a3 b in ) + a4 g out = (b1 r in ) + (b2 g in ) + ( b3 b in ) + b4 b out = (c1 r in ) + (c2 g in ) + (c3 b in ) + c4 0x26 read/write [4:0] ***00010 csc_b4_msb msb of r0x27. 0x27 read/write [7:0] 00011110 csc_b4_lsb csc coefficient for equation: r out = (a1 r in ) + (a2 g in ) + (a3 b in ) + a4 g out = (b1 r in ) + (b2 g in ) + (b3 b in ) + b4 b out = (c1 r in ) + (c2 g in ) + (c3 b in ) + c4 0x28 read/write [4:0] ***00000 cdc_c1_msb msb of r0x29. 0x29 read/write [7:0] 00000000 csc_c1_lsb csc coefficient for equation: r out = (a1 r in ) + (a2 g in ) + (a3 b in ) + a4 g out = (b1 r in ) + (b2 g in ) + (b3 b in ) + b4 b out = ( c1 r in ) + (c2 g in ) + (c3 b in ) + c4 0x2a read/write [4:0] ***00100 csc_c2_msb msb of r0x2b. 0x2b read/write [7:0] 10101000 csc_c2_lsb csc coefficient for equation: r out = (a1 r in ) + (a2 g in ) + (a3 b in ) + a4 g out = (b1 r in ) + (b2 g in ) + (b3 b in ) + b4 b out = (c1 r in ) + ( c2 g in ) + (c3 b in ) + c4 0x2c read/write [4:0] ***01000 csc_c3_msb msb of r0x2d. 0x2d read/write [7:0] 00010010 csc_c3_lsb csc coefficient for equation: r out = (a1 r in ) + (a2 g in ) + (a3 b in ) + a4 g out = (b1 r in ) + (b2 g in ) + (b3 b in ) + b4 b out = (c1 r in ) + (c2 g in ) + ( c3 b in ) + c4 0x2e read/write [4:0] ***11011 csc_c4_msb msb of r0x2f. 0x2f read/write [7:0] 10101100 csc_c4_lsb csc coefficient for equation: r out = (a1 r in ) + (a2 g in ) + (a3 b in ) + a4 g out = (b1 r in ) + (b2 g in ) + (b3 b in ) + b4 b out = (c1 r in ) + (c2 g in ) + (c3 b in ) + c4 0x30 read/write [7:0] 00000000 vfe_hs_pla_msb most significant 8 bits for hsync placement for itu 656 hsync regeneration. [7:6] 00****** vfe_hs_pla_lsb hsync placement lower 2 bits (see r0x30). 0x31 read/write [5:0] **000000 vfe_hs_dur_msb most significant 6 bits for hsync duration. [7:4] 0000**** vfe_hs_dur_lsb hsync duration lower 4 bits (see r0x31). 0x32 read/write [3:0] ****0000 vfe_vs_pla_msb most significant 4 bits for vsync placement for itu 656 vsync regeneration. [7:2] 000000** vfe_vs_pla_lsb vsync placement lower 6 bits (see r0x32). 0x33 read/write [1:0] ******00 vfe_vs_dur_msb most significant 2 bits for vsync duration. 0x34 read/write [7:0] 00000000 vfe_vs_dur_lsb vsync duration lower 8 bits (see r0x33). 0x35 read/write [7:0] 00000000 vfe_hsdelayin_msb most significant 8 bits for hsync delay in for itu 656 hsync regeneration. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 26 of 48 hex address read/write or read only bits default value register name description [7:6] 00****** vfe_hsdelayin_lsb hsync delay in lower 2 bits (see r0x35). 0x36 read/write [5:0] **000000 vfe_vsdelayin vsync delay in for de generation. [7:5] 000***** interlace offset sets the difference (in hsyncs) in field length between field 0 and field 1. 0x37 read/write [4:0] ***00000 vfe_width_msb most significant 5 bits for frame width. 0x38 read/write [7:1] 0000000* vfe_width lower 7 bits for frame width (see r0x37). 0x39 read/write [7:0] 00000000 vfe_height_msb most significant 8 bits for frame height. 0x3a read/write [7:4] 0000**** vfe_height lower 4 bits for frame height (see r0x39). [7] 1******* ext_audiosf_sel audio sampling frequency select. valid when using spdif input 0 = fs extracted from spdif 1 = fs set via r0x15[7:4] default = 1 (only used during pixel repetition mode). [6:5] *00***** pr_mode pixel repetition mode selection. set to b00 unless non-standard video is supported. 00 = auto mode. 01 = max mode. 1x = manual mode (see r0x3b bits [4:3]). default = 00. [4:3] ***00*** ext_pll_pr external value for pll pixel repetition. 00 = 1. 01 = 2. 10 = 4. 11 = 4. default = 00. [2:1] *****00* ext_target_pr user programmed pixel repetition number to send to rx. default = 00. 0x3b read/write [0] *******0 csc_en csc enable. 0 = no csc. 1 = enable csc. default = 0. 0x3c read/write [5:0] **000000 ext_vid_to_rx user programmed vid to send to rx. see table 24 for full vid formats. default = 0x00. [7:6] 00****** pr_to_rx the actual pixel repetition sent to rx. 0x3d read [5:0] **000000 vid_to_rx the actual vid sent to hdmi rx (see table 24). 0x3e read [7:2] 000000** vfe_fmt_vid vid detected by video fe (see table 24). [7:5] 000***** vfe_aux_vid this register is for video input formats that are not inside the 861b table. 000 = 480i not active. 001 = 240p not active. 010 = 576i not active. 011 = 288p not active. 100 = 480i active. 101 = 240p active. 110 = 576i active. 111 = 288p active. default = 000. 0x3f read [4:3] ***00*** vfe_prog_mode information about 240p and 288p. 240p C 01 = 262 lines. 240p C 10 = 263 lines. 288p C 01 = 312 lines. 288p C 10 = 313 lines. 288p C 11 = 314 lines. default = 00. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 27 of 48 hex address read/write or read only bits default value register name description [7] 0******* gc_pkt_en 1 = enable general control packet. default = 0. [6] *0****** spd_pkt_en 1 = enable source product descriptor packet. default = 0. [5] **0***** mpeg_pkt_en 1 = enable mpeg packet. default = 0. [4] ***0**** acp_pkt_en 1 = enable acp packet. default = 0. 0x40 read/write [3] ****0*** isrc_pkt_en 1 = enable isrc packet. default = 0. 0x41 read/write [6] *1****** system_pd 0 = all circuits powered up. 1 = power down the whole chip, except i 2 c, hpd interrupt and msen interrupt. default = 1. [5] **0***** test bit must be set to 0. [4] ***1**** intr_pol interrupt polarity. 0 = low active interrupt. 1 = high active interrupt. default = 1. [3] ****0*** initiate_scan 1 = initiate scan. default = 1. [7] 1******* pd_pol polarity for power-down pin. 0 = low active. 1 = high active. [6] *0****** hpd_state state of the hot plug detection. 0 = hot plug detect inactive. 1 = hot plug active. 0x42 read [5] **0***** msen_state state of the monitor connection. 0 = hdmi clock termination not detected. 1 = hdmi clock termination detected. 0x43 read/write [7:0] 01111110 edid_id the i 2 c address for edid memory. default = r0x7e. [7] 0******* spdif_en 1 = enable s/pdif receiver. default = 0. [6] *1****** n_cts_pkt_en 1 = enable n_cts packet. default = 1. [5] **1***** audio_sample_pkt_en 1 = enable audio sample packet. default = 1. [4] ***1**** aviif_pkt_en 1 = enable avi info frame. default = 1. 0x44 read/write [3] ****1*** audioif_pkt_en 1 = enable audio info frame. default = 1. [7] 0******* clear_avmute 1 = clear av mute. default = 0. [6] *0****** set_avmute 1 = set av mute. default = 0. [5:4] **00**** y1y0 output format, should be written when r0x16[7:6] is written. 00 = rgb. 01 = ycbcr 4:2:2. 10 = ycbcr 4:4:4. 11 = reserved. default = 00. [3] ****0*** active format information status active format information present. 0 = no data. 1 = active format information valid. default = 0. 0x45 read/write [2:1] *****00* bar information b[1:0]. 00 = no bar information. 01 = horizontal bar information valid. 10 = vertical bar information valid. 11 = horizontal and vertical bar information valid. default = 00. 0x46 read/write [7:6] 00****** scan information s[1:0]. 00 = no information. 01 = overscanned (television). 10 = underscanned (computer). 11 = undefined. default = 00. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 28 of 48 hex address read/write or read only bits default value register name description [5:4] **00**** colorimetry c[1:0]. 00 = no data. 01 = smpte 170m, itu601. 10 = itu709. 11 = undefined. default = 00. [3:2] ****00** picture aspect ratio m[1:0]. 00 = no data. 01 = 4:3. 10 = 16:9. 11 = undefined. default = 00. [1:0] ******00 nonuniform picture scaling sc[1:0]. 00 = no known nonuniform scaling. 01 = picture has been scaled horizontally. 10 = picture has been scaled vertically. 11 = picture has been scaled horizontally and vertically. default = 00. 0x47 read/write [7:4] 0000**** active format aspect ratio r[3:0]. 1000 = same as picture aspect ratio. 1001 = 4:3 (center). 1010 = 16:9 (center). 1011 = 14:9 (center). default = 0x0. 0x48 read/write [7:0] 00000000 active line start lsb 0x49 read/write [7:0] 00000000 active line start msb this represents the line number at the end of the top horizontal bar. if 0, ther e is no horizontal bar. 0x4a read/write [7:0] 00000000 active line end lsb 0x4b read/write [7:0] 00000000 active line end msb this represents the line number at the beginning of a lower horizontal bar. if greater than the number of active video lines, there is no lower horizontal bar.. 0x4c read/write [7:0] 00000000 active pixel start lsb 0x4d read/write [7:0] 00000000 active pixel start msb this represents the last pixel in a vertical pillar bar at the left side of the picture. if 0, there is no left bar. 0x4e read/write [7:0] 00000000 active pixel end lsb 0x4f read/write [7:0] 00000000 active pixel end msb this represents the first horizontal pixel in a vertical pillar bar at the right side of the picture. if greater than the maximum number of horizontal pixels, there is no vertical bar. [7:5] 000***** audio_if_cc channel count. 000 = refer to stream header. 001 = 2 channels. 010 = 3 channels. 111 = 8 channels. default = 000. [4] ***0**** audio_if_dm_inh down-mix inhibit. 0 = permitted or no information about this. 1 = prohibited. default = 0. 0x50 read/write [3:0] ****0000 level shift lsv[3:0]. level shift values with attenuation information. 0000 = 0 db attenuation. 0001 = 1 db attenuation. 1111 = 15 db attenuation. default = 0x0. 0x51 read/write [7:0] 00000000 speaker mapping ca[7:0]. speaker mapping or placement for up to 8 channels (see table 24). default = 0x00. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 29 of 48 hex address read/write or read only bits default value register name description 0x52 read/write [7:0] 00000000 source product description infoframe byte 1. (spd_b1) vendor name character 1 (vn1). 0x53 read/write [7:0] 00000000 spd_b2 vn2. 0x54 read/write [7:0] 00000000 spd_b3 vn3. 0x55 read/write [7:0] 00000000 spd_b4 vn4. 0x56 read/write [7:0] 00000000 spd_b5 vn5. 0x57 read/write [7:0] 00000000 spd_b6 vn6. 0x58 read/write [7:0] 00000000 spd_b7 vn7. 0x59 read/write [7:0] 00000000 spd_b8 vn8. 0x5a read/write [7:0] 00000000 spd_b9 product description character 1 (pd1). 0x5b read/write [7:0] 00000000 spd_b10 pd2. 0x5c read/write [7:0] 00000000 spd_b11 pd3. 0x5d read/write [7:0] 00000000 spd_b12 pd4. 0x5e read/write [7:0] 00000000 spd_b13 pd5. 0x5f read/write [7:0] 00000000 spd_b14 pd6. 0x60 read/write [7:0] 00000000 spd_b15 pd7. 0x61 read/write [7:0] 00000000 spd_b16 pd8. 0x62 read/write [7:0] 00000000 spd_b17 pd9. 0x63 read/write [7:0] 00000000 spd_b18 pd10. 0x64 read/write [7:0] 00000000 spd_b19 pd11. 0x65 read/write [7:0] 00000000 spd_b20 pd12. 0x66 read/write [7:0] 00000000 spd_b21 pd13. 0x67 read/write [7:0] 00000000 spd_b22 pd14. 0x68 read/write [7:0] 00000000 spd_b23 pd15. 0x69 read/write [7:0] 00000000 spd_b24 pd16. 0x6a read/write [7:0] 00000000 spd_b25 source device information code. code defines source, such as dvd or stb. default = 0x00. 0x6b read/write [7:0] 00000000 mpeg_b0 0x6c read/write [7:0] 00000000 mpeg_b1 0x6d read/write [7:0] 00000000 mpeg_b2 0x6e read/write [7:0] 00000000 mpeg_b3 mb[0]. lower byte of mpeg bit rate: hz. this is the lower 8 bits of 32 bits (4 bytes) that specify the mpeg bit rate in hz. mb[1]. mb[2]. mb[3] (upper byte). 0x6f read/write [7] 0******* mpeg_fr fr indicates new picture or repeat. 0 = new field or picture. 1 = repeated field. default = 0. 0x70 read/write [6:5] *00***** mpeg_mf mpeg frame indicator. mf[1:0] identifies whether frame is an i, b, or p picture. 00 = unknown. 01 = i picture. 10 = b picture. 11 = p picture. default = 00. 0x71 read/write [7:0] 00000000 audio content protection packet (acp) type acp type. 0 = generic audio. 1 = iec 60958-identified audio. 2 = dvd audio. 3 = reserved for sacd. default = 0x00. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 30 of 48 hex address read/write or read only bits default value register name description 0x72 read/write [7:0] 00000000 acp_byte1 audio content protection. [7:6] audio_copy_permission. [5:3] audio_copy_number. [2:1] quality. [0] transaction. [7] 0******* isrc1 continued international standard recording code continued (isrc1). indicates an isrc2 packet is being transmitted. 1 = the 2nd isrc packet is needed. default = 0. [6] *0****** isrc1_valid 0 = isrc1 status bits and pbs not valid. 1 = isrc1 status bits and pbs valid. default = 0. 0x73 read/write [5:3] **000*** isrc1 status these bits indicate beginning, middle, and end of a track. 001 = start. 010 = middle. 100 = end. default = 000. 0x74 read/write [7:0] 00000000 isrc1_pb0 isrc1 packet byte 0. 0x75 read/write [7:0] 00000000 isrc1_pb1 isrc1 packet byte 1. 0x76 read/write [7:0] 00000000 isrc1_pb2 isrc1 packet byte 2. 0x77 read/write [7:0] 00000000 isrc1_ pb3 isrc1 packet byte 3. 0x78 read/write [7:0] 00000000 isrc1_ pb4 isrc1 packet byte 4. 0x79 read/write [7:0] 00000000 isrc1_ pb5 isrc1 packet byte 5. 0x7a read/write [7:0] 00000000 isrc1_ pb6 isrc1 packet byte 6. 0x7b read/write [7:0] 00000000 isrc1_ pb7 isrc1 packet byte 7. 0x7c read/write [7:0] 00000000 isrc1_ pb8 isrc1 packet byte 8. 0x7d read/write [7:0] 00000000 isrc1_ pb9 isrc1 packet byte 9. 0x7e read/write [7:0] 00000000 isrc1_ pb10 isrc1 packet byte 10. 0x7f read/write [7:0] 00000000 isrc1_ pb11 isrc1 packet byte 11. 0x80 read/write [7:0] 00000000 isrc1_ pb12 isrc1 packet byte 12. 0x81 read/write [7:0] 00000000 isrc1_ pb13 isrc1 packet byte 13. 0x82 read/write [7:0] 00000000 isrc1_ pb14 isrc1 packet byte 14. 0x83 read/write [7:0] 00000000 isrc1_ pb15 isrc1 packet byte 15. 0x84 read/write [7:0] 00000000 isrc2_ pb0 isrc2 packet byte 0. 0x85 read/write [7:0] 00000000 isrc2_ pb1 isrc2 packet byte 1. 0x86 read/write [7:0] 00000000 isrc2_ pb2 isrc2 packet byte 2. 0x87 read/write [7:0] 00000000 isrc2_ pb3 isrc2 packet byte 3. 0x88 read/write [7:0] 00000000 isrc2_ pb4 isrc2 packet byte 4. 0x89 read/write [7:0] 00000000 isrc2_ pb5 isrc2 packet byte 5. 0x8a read/write [7:0] 00000000 isrc2_ pb6 isrc2 packet byte 6. 0x8b read/write [7:0] 00000000 isrc2_ pb7 isrc2 packet byte 7. 0x8c read/write [7:0] 00000000 isrc2_ pb8 isrc2 packet byte 8. 0x8d read/write [7:0] 00000000 isrc2_ pb9 isrc2 packet byte 9. 0x8e read/write [7:0] 00000000 isrc2_ pb10 isrc2 packet byte 10. 0x8f read/write [7:0] 00000000 isrc2_ pb11 isrc2 packet byte 11. 0x90 read/write [7:0] 00000000 isrc2_ pb12 isrc2 packet byte 12. 0x91 read/write [7:0] 00000000 isrc2_ pb13 isrc2 packet byte 13. 0x92 read/write [7:0] 00000000 isrc2_ pb14 isrc2 packet byte 14. 0x93 read/write [7:0] 00000000 isrc2_ pb15 isrc2 packet byte 15. 0x94 read/write [7:0] 11000000 mask1 mask for interrupt group1 (r0x96). www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 31 of 48 hex address read/write or read only bits default value register name description 0x95 read/write [7:6] 00****** mask2 mask for interrupt group 2 (r0x97[7:6]. [7] for hdcp error. [6] for bksv flag. [7] 0******* hpd_int interrupt for hot plug detect (hpd). [6] *0****** msen_int interrupt for monitor connection (msen). [5] **0***** vs_int interrupt for active vs edge. [4] ***0**** aud_fifo_full_int interrupt for audio fifo overflow. [3] ****0*** itu656_err_int interrupt for itu656 error. 0x96 read/write [2] *****0** edid_rdy_int interrupt for edid ready. [7] 0******* hdcp_err_int interrupt bit from hdcp master. [6] *0****** bksv_flag set to 1 to instruct the mpu to read the bksv or the edid mem for revocation list checking. 0x97 read/write [2] *****0** test bit must be written to 1 for proper operation. [7] 0****** must be written to 0 for proper operation. 0x98 read/write [3:0] ****0010 test bit must be written to 0x2 for proper operation. 0x9c read/write [7:0] test bits must be written to 0x3a for proper operation. 0x9d read/write [3:0] ****0*** test bits mu st be written to 1 for proper operation. 0xa2 read/write [7:0] test bits must be written to 0x87 for proper operation. 0xa3 read/write [7:0] test bits must be written to 0x87 for proper operation. [7] 0******* hdcp_desired hdcp encryption. 0 = input av content not to be encrypted. 1 = the input a/v content should be encrypted. default = 0. [4] ***1**** frame_enc frame encryption. 0 = the current frame should not be encrypted. 1 = the current frame should be encrypted. default = 1. 0xaf read/write [1] ******0* ext_hdmi_mode hdmi mode. 0 = dvi. 1 = hdmi. default = 0. 0xb0 read [7:0] 00000000 an_0 byte 0 of an. 0xb1 read [7:0] 00000000 an_1 byte 1 of an. 0xb2 read [7:0] 00000000 an_2 byte 2 of an. 0xb3 read [7:0] 00000000 an_3 byte 3 of an. 0xb4 read [7:0] 00000000 an_4 byte 4 of an. 0xb5 read [7:0] 00000000 an_5 byte 5 of an. 0xb6 read [7:0] 00000000 an_6 byte 6 of an. 0xb7 read [7:0] 00000000 an_7 byte 7 of an. [6] *0****** enc_on 1 = the av content is being encrypted. 0 = not encrypted. default = 0. [5] **0***** int_hdmi_mode digital mode. 1 = hdmi mode. 0 = dvi mode. [4] ***0**** keys_read_error 1 = hdcp key reading error. [7:5] 000***** edge select for input video clock. 011 = positive edge capture. 111 = negative edge capture. default = 000. 0xba read/write [4] ***0**** clk_delay must be written to 0 for proper operation. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 32 of 48 hex address read/write or read only bits default value register name description [7] 0*** **** bcaps hdmi reserved. [6] *0** **** repeater hdcp repeater. 0 = hdcp receiver is not repeater capable. 1 = hdcp receiver is repeater capable. [5] **0* **** ksv ready ksv fifo ready. 1 = hdcp receiver has compiled list of attached ksvs. [4] ***0 **** test bit must be written to 0 for proper operation. [3:2] **** 00** test bit reserved. [1] **** **0* hdcp support hdcp 1.1 features support. 0 = hdcp receiver does not support v. 1.1 features. 1 = hdcp receiver supports 1.1 features such as enhanced encryption status signaling (eess). 0xbe read [0] **** ***0 fast hdcp fast authentication. 0 = hdcp receiver not capable of fast authentication. 1 = hdcp receiver capable of receiving unencrypted video during the session re-authentication. 0xbf read [7:0] 00000000 bksv1 0xc0 read [7:0] 00000000 bksv2 0xc1 read [7:0] 00000000 bksv3 0xc2 read [7:0] 00000000 bksv4 0xc3 read [7:0] 00000000 bksv5 bksv read from rx by the hdcp controller 40 bits (5 bytes). 0xc4 read/write [7:0] 00000000 edid segment sets the e-ddc segment used by the edid fetch routine. [7] 0******* error flag error flag interrupt. [6] *0****** an stop an stop interrupt. [5] **0***** hdcp enabled hdcp enabled interrupt. [4] ***0**** edid ready flag edid ready interrupt. [3] ****0*** i 2 c interrupt i 2 c interrupt. [2] *****0** ri flag ri interrupt. [1] ******0* bksv update flag bksv update interrupt. 0xc5 read [0] *******0 pj flag pj interrupt. [4] ***0**** hdmi mode hdmi interrupt. [3] ****0*** hdcp requested hdcp requested interrupt. [2] *****0** rx sense rx sense interrupt. [1] ******0* eeprom read ok eeprom read interrupt. 0xc6 read [0] *******0 tmds output enabled tm ds output enabled interrupt. [7] 0******* bksv flag bksv flag. 0xc7 read/write [6:0] *0000000 bksv count bksv count. [7:4] 0000**** hdcp controller error hdcp controller error (see table 28). 0xc8 read [3:0] ****0000 hdcp controller state hdcp controller state. 0xc9 read/write [3:0] ****0011 edid tries number of times that the edid is read if unsuccessful. default = 0x3. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 33 of 48 2-wire serial control register detail chip identification 0x00bits[7:0] chip revision an 8-bit register that represents the silicon revision. 0x01bits[3:0] n[19:16] these are the most significant four bits of a 20-bit word used along with the 20-bit cts term in the receiver to regenerate the audio clock. 0x02bits[7:0] n[15-8] 0x03bits[7:0] [(7-0] 0x04bits[3:0] cts_int[19:16] these are the most significant four bits of a 20-bit word used along with the 20-bit n term in the receiver to regenerate the audio clock. this is the measured or internal cts. the internal or external cts can be selected via r0x0a bit 7. 0x05bits[7:0] cts_int[15:8] 0x06bits[7:0] cts_in[7:0] 0x07bits[3:0] ct_ext[19:16]) these are the most significant four bits of a 20-bit word used along with the 20-bit n term in the receiver to regenerate the audio clock. this is the external cts. the internal or external cts can be selected via r0x0a bit 7. 0x08bits[7:0] cts_ext[15:8] 0x09bits[7:0] cts_ext[7:0] 0x0abits[7] cts_sel when internal cts is selected, the cts is calculated by the AD9889. 0 = internal cts 1 = external cts 0x0abits[6:5] avg_mode 00 = no filter 01 = divide by 4 10 = divide by 8 11 = divide by 16 default = 10 0x0abit[4] audio_sel 0 = i 2 s 1 = s/pdif default = 0 0x0abit[3] mclk_sp if mclk is available for s/pdif, it is used for bit recovery; otherwise, internal circuitry is used. 1 = mclk active 0 = mclk inactive default = 0 0x0abit[2] mclk_i 2 s 1 = i 2 s mclk active 0 = i 2 s mclk inactive default = 0 if mclk is available for i 2 s, it is used for bit recovery; otherwise, internal circuitry is used. 0x0abits[1:0] mclk_ratio 00 = 128 fs 01 = 256 fs 10 = 384 fs 11 = 512 fs default = 01 0x0bbit[6] mclk_ pol 0 = rising edge 1 = falling edge default = 0 0x0bbit[5] flat_line 1 = flat line audio (audio sample not valid) 0 = normal default = 0 0x0cbits[5:2] i 2 s enable 0001 = i 2 s0 0010 = i 2 s1 0100 = i 2 s2 1000 = i 2 s3 default = 1111 for all 0x0cbits[1:0] i 2 s format 00 = standard i 2 s mode 01 = right-justified i 2 s mode 10 = left-justified i 2 s mode 11 = raw iec60958 mode default = 00 0x0dbits[4:0] i 2 s bit width for right-justified audio only. default is 11000 (24). not valid for widths greater than 24. 0x0ebits[5:3] subpkt0_l_src source of audio subpacket 0 (left channel) data. default is 000. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 34 of 48 table 23. source of subpacket audio field code channel (0 to 3) and left/right 000 channel 0 left 001 channel 0 right 010 channel 1 left 011 channel 1 right 100 channel 2 left 101 channel 2 right 110 channel 3 left 111 channel 3 right 0x0ebits[2:0] subpkt0_r_src default is 001 (see table 27). 0x0fbits[5:3] subpkt1_l_src default is 010 (see table 27). 0x0fbits[2:0] subpkt1_r_src default is 011 (see table 27). 0x10bits[5:3] subpkt2_l_src default is 100 (see table 27). 0x10bits[2:0] subpkt2_r_src default is 101 (see table 27). 0x11bits[5:3] subpkt3_l_src default is 110 (see table 27). 0x11bits[2:0] subpkt3_r_src default is 111 (see table 27). 0x18bits[4:0] csc_a1_msb these five bits form the 5 msbs of the color space conversion coefficient a1. combined with the 8 lsbs of the following register, they form a 13-bit, twos complement coefficient that is user programmable. the equation takes the form of r out = ( a1 r in ) + (a2 g in ) + (a3 b in ) + a4 g out = (b1 r in ) + (b2 g in ) + (b3 b in ) + b4 b out = (c1 r in ) + (c2 g in ) + (c3 b in ) + c4 the default value for the 13-bit, a1 coefficient is 0x0662. 0x19bits[7:0] csc_a1_lsb see register 0x18. 0x1abits[4:0] csc_a2_msb these five bits form the 5 msbs of the color space conversion coefficient a2. this combined with the 8 lsbs of the following register form a 13-bit, twos complement coefficient that is user programmable. the equation takes the form of r out = (a1 r in ) + ( a2 g in ) + (a3 b in ) + a4 g out = (b1 r in ) + (b2 g in ) + (b3 b in ) + b4 b out = (c1 r in ) + (c2 g in ) + (c3 b in ) + c4 the default value for the 13-bit a2 coefficient is 0x04a8. 0x1bbits[7:0] csc_a2_lsb see register 0x1a. 0x1cbits[4:0] csc_a3_msb the default value for the 13-bit a3 is 0x0000. 0x1dbits[7:0] csc_a3_lsb 0x1ebits[4:0] csc_a4_msb the default value for the 13-bit a4 is 0x1c84. 0x1fbits[7:0] csc_a4_lsb 0x20bits[4:0] csc_b1_msb the default value for the 13-bit b1 is 0x1cbf. 0x21bits[7:0] csc_b1_lsb 0x22bits[4:0] csc_b2_msb the default value for the 13-bit b2 is 0x04a8. 0x23bits[7:0] csc_b2_lsb 0x24bits[4:0] csc_b3_msb the default value for the 13-bit b3 is 0x1e70. 0x25bits[7:0] csc_b3_lsb 0x26bits[4:0] csc_b4_msb the default value for the 13-bit b4 is 0x021e. 0x27bits[7:0] csc_b4_lsb 0x28bits[4:0] csc_c1_msb the default value for the 13-bit c1 is 0x0000. 0x29bits[7:0] csc_c1_lsb 0x2abits[4:0] csc_c2_msb the default value for the 13-bit c2 is 0x04a8. 0x2bbits[7:0] csc_c2_lsb 0x2cbits[4:0] csc_c3_msb the default value for the 13-bit c3 is 0x0812. 0x2dbits[7:0] csc_c3_lsb 0x2ebits[4:0] csc_c4_msb the default value for the 13-bit c4 is 0x1bac. 0x2fbits[7:0] csc_c4_lsb www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 35 of 48 0x3cbits[5:0] ext_vid_to_rx table 24. vid format vertical refresh 1 480p ~60 hz 1 2 480p ~60 hz 3 480p ~60 hz 4 720p ~60 hz 5 1080i ~60 hz 6 480i ~60 hz 7 480i ~60 hz 8 240p ~60 hz 9 240p ~60 hz 10 480i ~60 hz 11 480i ~60 hz 12 240p ~60 hz 13 240p ~60 hz 14 480p ~60 hz 15 480p ~60 hz 16 1080p ~60 hz 17 576p ~50 hz 2 18 576p ~50 hz 19 720p ~50 hz 20 1080i ~50 hz 21 576i ~50 hz 22 576i ~50 hz 23 288p ~50 hz 24 288p ~50 hz 25 576i ~50 hz 26 576i ~50 hz 27 288p ~50 hz 28 288p ~50 hz 29 576p ~50 hz 30 576p ~50 hz 31 1080p ~50 hz 32 1080p 24 hz to 30 hz 33 1080p 24 hz to 30 hz 34 1080p 24 hz to 30 hz 1 v ref can range from 59.826 hz to 60.115 hz. 2 v ref can range from 49.761 hz to 50.080 hz. 0x3dbits[7:6] pr_to_rx 0x43bits[7:0] edid read address this is a programmable i 2 c address from which the edid information (1 to 256 segment) can be read. default is 0x7e. 0x48bits[7:0] active line start lsb combined with the msb in register 0x49, these bits indicate the beginning line of active video. all lines before this comprise a top horizontal bar. this is used in letter-box modes. if the 2-byte value is 0x00, there is no horizontal bar. 0x49bits[7:0] active line start msb see register 0x48. 0x4abits[7:0] active line end lsb combined with the msb in register 0x4b, the bits indicate the last line of active video. all lines past this comprise a lower horizontal bar. this is used in letter-box modes. if the 2-byte value is greater than the number of lines in the display, there is no lower horizontal bar. 0x4bbits[7:0] active line end msb see register 0x4a. 0x4cbits[7:0] active pixel start lsb combined with the msb in register 0x4d, these bits indicate the first pixel in the display that is active video. all pixels before this comprise a left vertical bar. if the 2-byte value is 0x00, there is no left bar. 0x4dbits[7:0] active pixel start msb see register 0x4c. 0x4ebits[7:0] active pixel end lsb combined with the msb in register 0x4f, these bits indicate the last active video pixel in the display. all pixels past this comprise a right vertical bar. if the 2-byte value is greater than the number of pixels in the display, there is no vertical bar. 0x4fbits[7:0] active pixel end msb see register 0x4e. 05675-009 line1, pixel 1 4:3 display top horizontal bar bottom horizontal bar active line start r0x48, r0x49 active line end r0x4a, r0x4b figure 9. horizontal bars 05675-010 line1, pixel 1 4:3 display left vertical bar right vertical bar a ctive pixel end r0x4e, r0x4f a ctive pixel start r0x4c, r0x4d figure 10. vertical bars www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 36 of 48 0x50bits[7:5] audio_if_cc 000 = refer to stream header 001 = 2 channels 010 = 3 channels 111 = 8 channels 0x50bits[4] audi_if_dm_inh 0x50bits[3:0] level shift lsv[3:0] C level shift values with attenuation information. 0000 = 0 db attenuation 0001 = 1 db attenuation 1111 = 15 db attenuation default = 0x0 0x51bits[7:0] speaker mapping these bits define the suggested placement of speakers. table 25. ca channel number bit 4 bit 3 bit 2 bit 1 bit 0 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 0 0 0 0 0 - - fr fl 0 0 0 0 1 - lfe fr fl 0 0 0 1 0 fc - fr fl 0 0 0 1 1 fc lfe fr fl 0 0 1 0 0 rc - - fr fl 0 0 1 0 1 rc - lfe fr fl 0 0 1 1 0 rc fc - fr fl 0 0 1 1 1 rc fc lfe fr fl 0 1 0 0 0 rr rl - - fr fl 0 1 0 0 1 rr rl - lfe fr fl 0 1 0 1 0 rr rl fc - fr fl 0 1 0 1 1 - - rr rl fc lfe fr fl 0 1 1 0 0 - rc rr rl - - fr fl 0 1 1 0 1 - rc rr rl - lfe fr fl 0 1 1 1 0 - rc rr rl fc - fr fl 0 1 1 1 1 - rc rr rl fc lfe fr fl 1 0 0 0 0 rrc rlc rr rl - - fr fl 1 0 0 0 1 rrc rlc rr rl - lfe fr fl 1 0 0 1 0 rrc rlc rr rl fc - fr fl 1 0 0 1 1 rrc rlc rr rl fc lfe fr fl 1 0 1 0 0 frc flc - - - - fr fl 1 0 1 0 1 frc flc - - - lfe fr fl 1 0 1 1 0 frc flc - - fc - fr fl 1 0 1 1 1 frc flc - - fc lfe fr fl 1 1 0 0 0 frc flc - rc - - fr fl 1 1 0 0 1 frc flc - rc - lfe fr fl 1 1 0 1 0 frc flc - rc fc - fr fl 1 1 0 1 1 frc flc - rc fc lfe fr fl 1 1 1 0 0 frc flc rr rl - - fr fl 1 1 1 0 1 frc flc rr rl - lfe fr fl 1 1 1 1 0 frc flc rr rl fc - fr fl 1 1 1 1 1 frc flc rr rl fc lfe fr fl www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 37 of 48 source product description (spd) infoframe 0x52bits[7:0] spd_b1 this is the first character in eight (vn1-vn8) that is the name of the company that appears on the product. the data characters are 7-bit ascii code. 0x53bits[7:0] spd_b 2 (vn2) 0x54bits[7:0] spd_b 3(vn3) 0x55bits[7:0] spd_b 4(vn4) 0x56bits[7:0] spd_b 5(vn5) 0x57bits[7:0] spd_b 6(vn6) 0x58bits[7:0] spd_b 7(vn7) 0x59bits[7:0] spd_b 8(vn8) 0x5abits[7:0] sbd_b9 product description character 1 (pd1) this is the first character of 16 that contains the model number and a short description of the product. the data characters are 7-bit ascii code. 0x5bbits[7:0] sbd_b10(pd2) 0x5cbits[7:0] sbd_b11(pd3) 0x5dbits[7:0] sbd_b12(pd4) 0x5ebits[7:0] sbd_b13(pd5) 0x5fbits[7:0] sbd_b14(pd6) 0x60bits[7:0] sbd_b15(pd7) 0x61bits[7:0] sbd_b16(pd8) 0x62bits[7:0] sbd_b17(pd9) 0x63bits[7:0] sbd_b18(pd10) 0x64bits[7:0] sbd_b19(pd11) 0x65bits[7:0] sbd_b20(pd12) 0x66bits[7:0] sbd_b21(pd13) 0x67bits[7:0] sbd_b22(pd14) 0x68bits[7:0] sbd_b23(pd15) 0x69bits[7:0] sbd_b24(pd16) 0x6abits[7:0] source device information code these bytes classify the source device. table 26. sdi code source 0x00 unknown 0x01 digital stb 0x02 dvd 0x03 d-vhs 0x04 hdd video 0x05 dvc 0x06 dsc 0x07 video cd 0x08 game 0x09 pc general 0x0a to 0xff reserved 0x6bbits[7:0] mpeg_b0 this is the lower 8 bits of 32 bits that specify the mpeg bit rate in hz. 0x6cbits[7:0] mpeg_b1 0x6dbits[7:0] mpeg_b2 0x6ebits[7:0] mpeg_b3 0x73bits[7] isrc1 continued this bit indicates that a continuation of the 16 isrc1 packet bytes (an isrc2 packet) is being transmitted. 0x73bit[6] isrc1 valid this bit indicates whether isrc1 packet bytes are valid. table 27. isrc1 valid 0 isrc1 status bits and pbs not valid 1 isrc1 status bits and pbs valid 0x73bits[5:3] isrc1 status these bits define where the samples are in the isrc track: at least two transmissions of 001 occur at the beginning of the track; continuous transmission of 010 occurs in the middle of the track, followed by at least two transmissions of 100 near the end of the track. 0x74bits[7:0] isrc1_pb0 0x75bits[7:0] isrc1_pb1 0x76bits[7:0] isrc1_pb2 0x77bits[7:0] isrc1_pb3 0x78bits[7:0] isrc1_pb4 0x79bits[7:0] isrc1_pb5 0x7abits[7:0] isrc1_pb6 0x7bbits[7:0] isrc1_pb7 0x7cbits[7:0] isrc1_pb8 0x7dbits[7:0] isrc1_pb9 0x7ebits[7:0] isrc1_pb10 0x7fbits[7:0] isrc1_pb11 0x80bits[7:0] isrc1_pb12 0x81bits[7:0] isrc1_pb13 0x82bits[7:0] isrc1_pb14 0x83bits[7:0] isrc1_pb15 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 38 of 48 0x84bits[7:0] isrc2_pb0 this is transmitted only when the isrc continue bit (register 0x73 bit 7) is set to 1. 0x85bits[7:0] isrc2_pb1 0x86bits[7:0] isrc2_pb2 0x87bits[7:0] isrc2_pb3 0x88bits[7:0] isrc2_pb4 0x89bits[7:0] isrc2_pb5 0x8abits[7:0] isrc2_pb6 0x8bbits[7:0] isrc2_pb7 0x8cbits[7:0] isrc2_pb8 0x8dbits[7:0] isrc2_pb9 0x8ebits[7:0] isrc2_pb10 0x8fbits[7:0] isrc2_pb11 0x90bits[7:0] isrc2_pb12 0x91bits[7:0] isrc2_pb13 0x92bits[7:0] isrc2_pb14 0x93bits[7:0] isrc2_pb15 0x94bits[7:0] mask1 0x95bits[7:6] mask2 0x96bit[7] hpd_int 0x96bit[6] msen_int 0x96bit[5] vs_int 0x96bit[4]aud_fifo_full_int 0x96bit[3] itu656_err_int 0x96bit[2] edid_rdy_int 0x97bit[7] hdcp_err_int 0x97bit[6] bksv_flag 0x97bit[2] 0x98bit[7] 0x98bits[3:0] 0x9cbits[7:0] 0x9dbits[3:0] 0xa2bits[7:0] 0xa3bits[7:0] 0xafbit[7] hdcp_desired 0xafbit[4] frame_enc 0xafbit[1] ext_hdmi_mode 0xb0bits[7:0] an_0 0xb1bits[7:0] an_1 0xb2bits[7:0] an_2 0xb3bits[7:0] an_3 0xb4bits[7:0] an_4 0xb5bits[7:0] an_5 0xb6bits[7:0] an_6 0xb7bits[7:0] an_7 0xb7bit[6] enc_on 0xb7bit[5] int_hdmi_mode 0xb7bit[4] keys_read_error 0xbabits[7:5] clk_delay 0xbabit[4] clk_delay 0xbebit[7] bcaps 0xbebit[6] 0xbebit[5] 0xbebit[4] 0xbebits[3:2] 0xbebit[1] 0xbebit[0] 0xbfbits[7:0] bksv1 0xc0bits[7:0] bksv byte2 0xc1bits[7:0] bksv3 0xc2bits[7:0] bksv4 0xc3bits[7:0] bksv5 0xc4bits[7:0] edid segment these bits support up to 256 edid segments that can be addressed. the requested segment address is written here before initiation of the read. 0xc5bit[7] errorflag interrupt 0xc5bit[6] an stop interrupt 0xc5bit[5] hdcp enabled interrupt 0xc5bit[4] edid ready interrupt 0xc5bit[3] i 2 c interrupt 0xc5bit[2] ri interrupt 0xc5bit[1] bksv update interrupt 0xc5bit[0] pj interrupt 0xc6bit[4] hdmi mode interrupt 0xc6bit[3] hdcp requested interrupt 0xc6bit[2] rx sense interrupt 0xc6bit[1] eeprom read interrupt 0xc7bit[7] bksv flag 0xc7bits[6:0] bksv count www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 39 of 48 0xc8bits[7:4] hdcp controller error when an error occurs in the hdcp flow, it is reported here after setting the error flag (0xc5[7]). table 28. error code error condition 0000 no error 0001 bad receiver bksv 0010 ri mismatch 0011 pj mismatch 0100 i 2 c error (usually a no acknowledge) 0101 timed out waiting for downstream repeater 0110 maximum cascade of repeaters exceeded 0111 sha-1 hash check of bksv list failed 1000 too many devices connected to repeater tree 0xc8bits[3:0] hdcp controller state this information is used in troubleshooting the hdcp controller. 0xc9bits[3:0] edid read tries these bits define the number of times the edid attempts to be read if unsuccessful. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 40 of 48 2-wire serial control port a 2-wire serial interface is provided. up to two AD9889 devices can be connected to the 2-wire serial interface, with each device having a unique address. the 2-wire serial interface comprises a clock (scl) and a bidirectional data (sda) pin. the analog flat panel interface acts as a slave for receiving and transmitting data over the serial interface. when the serial interface is not active, the logic levels on scl and sda are pulled high by external pull-up resistors. data received or transmitted on the sda line must be stable for the duration of the positive going scl pulse. data on sda must change only when scl is low. if sda changes state while scl is high, the serial interface interprets that action as a start or stop sequence. there are five components to serial bus operation: ? start signal ? slave address byte ? base register address byte ? data byte to read or write ? stop signal when the serial interface is inactive (scl and sda are high) communications are initiated by sending a start signal. the start signal is a high-to-low transiti on on sda while scl is high. this signal alerts all slave devices that a data transfer sequence is coming. the first 8 bits of data transferred after a start signal comprise a 7-bit slave address (the first 7 bits) and a single r/ w bit (the eighth bit). the r/ w bit indicates the direction of data transfer, read from (1) or write to (0) the slave device. if the transmitted slave address matches the address of the device, the AD9889 acknowledges by bringing sda low on the ninth scl pulse. if the addresses do not match, the AD9889 does not acknowledge. table 29. serial port addresses bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 a 6 (msb) a 5 a 4 a 3 a 2 a 1 a 0 0 1 1 1 0 0 0 0 1 1 1 0 0 1 data transfer via serial interface for each byte of data read or written, the msb is the first bit of the sequence. if the AD9889 does not acknowledge the master device during a write sequence, the sda remains high so the master can generate a stop signal. if the master device does not acknowl- edge the AD9889 during a read sequence, the AD9889 inter- prets this as the end of data. the sda remains high so the master can generate a stop signal. writing data to specific control registers of the AD9889 re- quires that the 8-bit address of the control register of interest be written to after the slave address has been established. this control register address is the base address for subsequent write operations. the base address auto-increments by one for each byte of data written after the data byte intended for the base address. data is read from the control registers of the AD9889 in a similar manner. reading requires two data transfer operations: ? the base address must be written with the r/ w bit of the slave address byte low to set up a sequential read operation. ? reading (the r/ w bit of the slave address byte high) begins at the previously established base address. the address of the read register auto-increments after each byte is transferred. to terminate a read/write sequence to the AD9889, a stop signal must be sent. a stop signal comprises a low-to-high transition of sda while scl is high. a repeated start signal occurs when the master device driving the serial interface generates a start signal without first generating a stop signal to terminate the current communication. this is used to change the mode of communication (read, write) between the slave and master without releasing the serial interface lines. 05675-011 sda scl t buff t stah t dho t dsu t dal t dah t stasu t stosu figure 11. serial port read/write timing www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 41 of 48 serial interface read/write examples write to one control register: ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? data byte to base address ? stop signal ? write to four consecutive control registers ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? data byte to base address ? data byte to (base address + 1) ? data byte to (base address + 2) ? data byte to (base address + 3) ? stop signal read from one control register: ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? start signal ? slave address byte (r/ w bit = high) ? data byte from base address ? stop signal read from four consecutive control registers: ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? start signal ? slave address byte (r/ w bit = high) ? data byte from base address ? data byte from (base address + 1) ? data byte from (base address + 2) ? data byte from (base address + 3) ? stop signal 05675-012 bit 7 ack bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 s da scl figure 12. serial interfacetypical byte transfer www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 42 of 48 pcb layout recommendations the AD9889 is a high precision, high speed analog device. as such, to get the maximum performance out of the part, it is important to have a well laid out board. the following is a guide for designing a board using the AD9889. power supply bypassing it is recommended to bypass each power supply pin with a 0.1 f capacitor. the exception is when two or more supply pins are adjacent to each other. for these groupings of powers/grounds, it is necessary to have only one bypass capacitor. the fundamental idea is to have a bypass capacitor within about 0.5 cm of each power pin. also, avoid placing the capacitor on the opposite side of the pc board from the AD9889, as that interposes resistive vias in the path. the bypass capacitors should be physically located between the power plane and the power pin. current should flow from the power plane to the capacitor to the power pin. do not make the power connection between the capacitor and the power pin. placing a via underneath the capacitor pads, down to the power plane, is generally the best approach. it is particularly important to maintain low noise and good stability of pv d (the clock generator supply). abrupt changes in pv d can result in similarly abrupt changes in sampling clock phase and frequency. this can be avoided by careful attention to regulation, filtering, and bypassing. it is highly desirable to provide separate regulated supplies for each of the analog circuitry groups (v d and pv d ). some graphic controllers use substantially different levels of power when active (during active picture time) and when idle (during horizontal and vertical sync periods). this can result in a measurable change in the voltage supplied to the analog supply regulator, which can in turn produce changes in the regulated analog supply voltage. this can be mitigated by regulating the analog supply, or at least pv d , from a different, cleaner power source (for example, from a 12 v supply). it is also recommended to use a single ground plane for the entire board. experience has shown repeatedly that noise performance is the same or better with a single ground plane. using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result. in some cases, using separate ground planes is unavoidable, so it is recommended to place a single ground plane under the AD9889. the location of the split should be at the receiver of the digital outputs. for this case, it is even more important to place components wisely because the current loops are much longer (current takes the path of least resistance). figure 13 shows an example of a current loop. a n a l o g g r o u n d p l a n e p o w e r p l a n e a d 9 8 8 9 d i g i t a l o u t p u t t r a c e d i g i t a l g r o u n d p l a n e d i g i t a l d a t a r e c e i v e r 05675-013 figure 13. current loop digital inputs the digital inputs on the AD9889 were designed to work with 1.8 v signals but are tolerant of 3.3 v signals. therefore, no extra components need to be added if using 3.3 v logic. any noise that gets onto the hsync input trace adds jitter to the system. therefore, minimize the trace length and do not run any digital or other high frequency traces near it. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 43 of 48 color space converter (csc) common settings table 30. hdtv ycbcr (0 to 255) to rgb (0 to 255) (default setting for AD9889) register red/cr coeff 1 red/cr coeff 2 red/cr coeff 3 red/cr offset address 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f value 0x0c 0x52 0x08 0x 00 0x00 0x00 0x19 0xd7 register green/y coeff 1 green/y coeff 2 green/y coeff 3 green/y offset address 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 value 0x1c 0x54 0x08 0x 00 0x3e 0x89 0x02 0x91 register blue/cb coeff 1 blue/cb coeff 2 blue/cb coeff 3 blue/cb offset address 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f value 0x00 0x00 0x08 0x00 0x0e 0x87 0x18 0xbd table 31. hdtv ycbcr (16 to 235) to rgb (0 to 255) register red/cr coeff 1 red/cr coeff 2 red/cr coeff 3 red/cr offset address 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f value 0x47 0x2c 0x04 0xa8 0x00 0x00 0x1c 0x1f register green/y coeff 1 green/y coeff 2 green/y coeff 3 green/y offset address 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 value 0x1d 0xdd 0x04 0x a8 0x1f 0x26 0x01 0x34 register blue/cb coeff 1 blue/cb coeff 2 blue/cb coeff 3 blue/cb offset address 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f value 0x00 0x00 0x04 0xa8 0x08 0x 75 0x1b 0x7b table 32. sdtv ycbcr (0 to 255) to rgb (0 to 255) register red/cr coeff 1 red/cr coeff 2 red/cr coeff 3 red/cr offset address 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f value 0x2a 0xf8 0x08 0x00 0x00 0x00 0x1a 0x84 register green/y coeff 1 green/y coeff 2 green/y coeff 3 green/y offset address 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 value 0x1a 0x6a 0x08 0x00 0x1d 0x50 0x04 0x23 register blue/cb coeff. 1 blue/cb coeff 2 blue/cb coeff 3 blue/cb offset address 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f value 0x00 0x00 0x08 0x00 0x0d 0xdb 0x19 0x12 table 33. sdtv ycbcr (16 to 235) to rgb (0 to 255) register red/cr coeff 1 red/cr coeff 2 red/cr coeff 3 red/cr offset address 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f value 0x46 0x63 0x04 0xa8 0x00 0x00 0x1c 0x84 register green/y coeff 1 green/y coeff 2 green/y coeff 3 green/y offset address 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 value 0x1c 0xc0 0x04 0xa8 0x1e 0x6f 0x02 0x1e register blue/cb coeff 1 blue/cb coeff 2 blue/cb coeff 3 blue/cb offset address 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f value 0x00 0x00 0x04 0xa8 0x08 0x11 0x1b 0xad www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 44 of 48 table 34. rgb (0 to 255) to hdtv ycbcr (0 to 255) register red/cr coeff 1 red/cr coeff 2 red/cr coeff 3 red/cr offset address 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f value 0x08 0x2d 0x18 0x93 0x1f 0x3f 0x08 0x00 register green/y coeff 1 green/y coeff 2 green/y coeff 3 green/y offset address 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 value 0x03 0x68 0x0b 0x71 0x01 0x27 0x00 0x00 register blue/cb coeff 1 blue/cb coeff 2 blue/cb coeff 3 blue/cb offset address 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f value 0x1e 0x21 0x19 0xb2 0x08 0x2d 0x08 0x00 table 35. rgb (0 to 255) to hdtv ycbcr (16 to 235) register red/cr coeff 1 red/cr coeff 2 red/cr coeff 3 red/cr offset address 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f value 0x07 0x06 0x19 0xa0 0x1f 0x5b 0x08 0x00 register green/y coeff 1 green/y coeff 2 green/y coeff 3 green/y offset address 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 value 0x02 0xed 0x09 0x d3 0x00 0xfd 0x01 0x00 register blue/cb coeff 1 blue/cb coeff 2 blue/cb coeff 3 blue/cb offset address 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f value 0x1e 0x64 0x1a 0x96 0x07 0x06 0x08 0x00 table 36. rgb (0 to 255) to sdtv ycbcr (0 to 255) register red/cr coeff 1 red/cr coeff 2 red/cr coeff 3 red/cr offset address 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f value 0x08 0x2d 0x19 0x 27 0x1e 0xac 0x08 0x00 register green/y coeff 1 green/y coeff 2 green/y coeff 3 green/y offset address 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 value 0x04 0xc9 0x09 0x 64 0x01 0xd3 0x00 0x00 register blue/cb coeff 1 blue/cb coeff 2 blue/cb coeff 3 blue/cb offset address 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f value 0x1d 0x3f 0x1a 0x93 0x08 0x2d 0x08 0x00 table 37. rgb (0 to 255) to sdtv ycbcr (16 to 235) register red/cr coeff 1 red/cr coeff 2 red/cr coeff 3 red/cr offset address 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f value 0x07 0x06 0x1a 0x1e 0x1e 0xdc 0x08 0x00 register green/y coeff 1 green/y coeff 2 green/y coeff 3 green/y offset address 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 value 0x04 0x1c 0x08 0x11 0x01 0x91 0x01 0x00 register blue/cb coeff 1 blue/cb coeff 2 blue/cb coeff 3 blue/cb offset address 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f value 0x1d 0xa3 0x1b 0x57 0x07 0x06 0x08 0x00 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 45 of 48 outline dimensions compliant to jedec standards ms-026-bec 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.10 max coplanarity view a rotated 90 ccw seating plane 7 3.5 0 61 60 1 80 20 41 21 40 view a 1.60 max 0.75 0.60 0.45 16.20 16.00 sq 15.80 14.20 14.00 sq 13.80 0.65 bsc lead pitch 0.38 0.32 0.22 top view (pins down) pin 1 figure 14. 80-lead low profile quad flat package [lqfp] (st-80-2) dimensions shown in millimeters ordering guide model temperature range package description package option AD9889kstz-80 1 0c to 70c 80-lead low profile quad flat package (lqfp) st-80-2 AD9889/pcb evaluation board 1 z = pb-free part. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 46 of 48 notes www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 47 of 48 notes www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
AD9889 rev. 0 | page 48 of 48 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05675-0-10/05(0) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet

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